A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
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1. A vertical transistor comprising: a fin or nanowire disposed over a semiconductor substrate; a gate electrode formed over sidewalls of the fin or nanowire; a bottom source/drain contact adjacent to the gate electrode; a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap; and a bottom source/drain region located between the fin or the nanowire and a top semiconductor layer of the semiconductor substrate, the bottom source/drain region is laterally separated from the bottom source/drain contact by a bottom spacer.
A vertical transistor consists of a fin or nanowire on top of a semiconductor substrate. A gate electrode surrounds the sides of the fin or nanowire. A bottom source/drain contact sits next to the gate electrode. A dielectric spacer, containing a vertical air-gap, is positioned between the gate electrode and the bottom source/drain contact. A bottom source/drain region is located between the fin/nanowire and the semiconductor substrate's top layer and it's laterally separated from the bottom source/drain contact by a bottom spacer. This design aims to reduce parasitic capacitance.
2. The vertical transistor of claim 1 , wherein a topmost surface of the bottom spacer is coplanar with a topmost surface of the bottom source/drain region.
In the vertical transistor described, where there's a fin or nanowire on a semiconductor substrate, a gate electrode around the fin/nanowire's sides, a bottom source/drain contact next to the gate, a dielectric spacer (with a vertical air-gap) between the gate and contact, and a bottom source/drain region (laterally separated by a bottom spacer), the topmost surface of the bottom spacer aligns with the topmost surface of the bottom source/drain region. This coplanar arrangement simplifies fabrication and improves electrical performance.
3. The vertical transistor of claim 1 , wherein the vertical air-gap present within the dielectric spacer is disposed above a portion of the bottom spacer located below the gate electrode.
In the vertical transistor described, where there's a fin or nanowire on a semiconductor substrate, a gate electrode around the fin/nanowire's sides, a bottom source/drain contact next to the gate, a dielectric spacer (with a vertical air-gap) between the gate and contact, and a bottom source/drain region (laterally separated by a bottom spacer), the vertical air-gap within the dielectric spacer is located above a portion of the bottom spacer that sits underneath the gate electrode. This placement of the air gap minimizes capacitance between the gate and the source/drain region.
4. The vertical transistor of claim 1 , wherein the dielectric spacer further contains a horizontal air-gap, said horizontal air-gap is disposed below a bottommost surface of the gate electrode and is separated from the bottom source/drain region by the bottom spacer.
A vertical transistor includes a fin or nanowire on a semiconductor substrate, a gate electrode around the fin/nanowire's sides, a bottom source/drain contact next to the gate, and a dielectric spacer between the gate and contact. This dielectric spacer has both a vertical air-gap and a horizontal air-gap. The horizontal air-gap is located below the bottom edge of the gate electrode and is separated from the bottom source/drain region by the bottom spacer. This dual air-gap design further reduces parasitic capacitance.
5. The vertical transistor of claim 4 , wherein the horizontal air-gap of the dielectric spacer is interconnected with the vertical air-gap of the dielectric spacer.
The vertical transistor with a fin or nanowire on a semiconductor substrate, a gate electrode, a bottom source/drain contact, and a dielectric spacer containing both vertical and horizontal air-gaps, the horizontal air-gap and the vertical air-gap are connected. This interconnection creates a larger overall air gap, enhancing the reduction of parasitic capacitance and improving transistor performance by minimizing unwanted electrical coupling between the gate and the source/drain contact.
6. The vertical transistor of claim 1 , wherein the vertical air-gap present within the dielectric spacer is disposed below a topmost surface of the gate electrode.
In the vertical transistor which has a fin or nanowire disposed over a semiconductor substrate, a gate electrode formed over sidewalls of the fin or nanowire, a bottom source/drain contact adjacent to the gate electrode, a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap, the vertical air-gap resides below the top surface of the gate electrode. This placement ensures proper electrical isolation.
7. The vertical transistor of claim 6 , wherein the vertical air-gap height is 30 to 95% of a height of the gate electrode.
The vertical transistor featuring a fin or nanowire on a semiconductor substrate, a gate electrode, a bottom source/drain contact, and a dielectric spacer with a vertical air-gap, where the vertical air-gap sits below the top of the gate electrode, has a vertical air-gap height that's 30% to 95% of the gate electrode's height. This specific air-gap height range optimizes the balance between capacitance reduction and structural integrity of the device.
8. The vertical transistor of claim 1 , wherein a distance between the gate electrode and the bottom source/drain contact is from 4 nm to 20 nm.
A vertical transistor consists of a fin or nanowire on a semiconductor substrate, a gate electrode surrounding the sides of the fin or nanowire, a bottom source/drain contact sitting next to the gate electrode, and a dielectric spacer (containing a vertical air-gap) between the gate electrode and the bottom source/drain contact, the distance between the gate electrode and the bottom source/drain contact is from 4 nm to 20 nm. This narrow spacing contributes to improved transistor switching speed and performance.
9. The vertical transistor of claim 1 , wherein the vertical air-gap height is from 15 nm to 50 nm and the vertical air-gap width is from 4 nm to 20 nm.
A vertical transistor includes a fin or nanowire on a semiconductor substrate, a gate electrode around the fin/nanowire's sides, a bottom source/drain contact next to the gate, and a dielectric spacer between the gate and contact. The dielectric spacer contains a vertical air-gap with a height between 15 nm and 50 nm and a width between 4 nm and 20 nm. This specified dimension range optimizes capacitance reduction while maintaining structural stability and manufacturability.
10. The vertical transistor of claim 1 , further comprising a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact.
The vertical transistor which includes a fin or nanowire disposed over a semiconductor substrate, a gate electrode formed over sidewalls of the fin or nanowire, a bottom source/drain contact adjacent to the gate electrode, a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap, also has a conformal dielectric layer that touches the exposed surfaces of both the gate electrode and the bottom source/drain contact. This conformal layer provides further electrical insulation and protection against shorting.
11. A vertical transistor comprising: a fin or nanowire disposed over a semiconductor substrate; a gate electrode formed over sidewalls of the fin or nanowire; a bottom source/drain contact adjacent to the gate electrode; a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap; a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact; and a bottom source/drain region located between the fin or nanowire and a top semiconductor layer of the semiconductor substrate, wherein the conformal dielectric layer is separated from the bottom source/drain region by a bottom spacer.
A vertical transistor is formed by a fin or nanowire disposed over a semiconductor substrate; a gate electrode formed over sidewalls of the fin or nanowire; a bottom source/drain contact adjacent to the gate electrode; a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap; a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact; and a bottom source/drain region located between the fin or nanowire and a top semiconductor layer of the semiconductor substrate, wherein the conformal dielectric layer is separated from the bottom source/drain region by a bottom spacer. This complex structure isolates components and reduce parasitic capacitance.
12. The vertical transistor of claim 11 , further comprising a gate dielectric between the sidewall of the fin or the nanowire and the gate electrode, the gate dielectric extending below a bottommost surface of the gate electrode, wherein the conformal dielectric layer contacts a bottommost surface of the gate dielectric.
The vertical transistor which has a fin or nanowire disposed over a semiconductor substrate, a gate electrode formed over sidewalls of the fin or nanowire, a bottom source/drain contact adjacent to the gate electrode, a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap; a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact; and a bottom source/drain region located between the fin or nanowire and a top semiconductor layer of the semiconductor substrate, wherein the conformal dielectric layer is separated from the bottom source/drain region by a bottom spacer; also includes a gate dielectric between the fin/nanowire sidewall and the gate electrode. This gate dielectric extends below the gate electrode's bottom edge, and the conformal dielectric layer touches the bottom surface of the gate dielectric, improving gate control.
13. The vertical transistor of claim 1 , wherein the dielectric spacer comprises a dielectric material selected from the group consisting of amorphous carbon, a carbon-doped oxide, a fluorine-doped oxide, SiCOH and SiBCN.
In the vertical transistor described, where there's a fin or nanowire on a semiconductor substrate, a gate electrode around the fin/nanowire's sides, a bottom source/drain contact next to the gate, a dielectric spacer (with a vertical air-gap) between the gate and contact, and a bottom source/drain region (laterally separated by a bottom spacer), the material forming the dielectric spacer is chosen from amorphous carbon, a carbon-doped oxide, a fluorine-doped oxide, SiCOH, or SiBCN. These materials offer specific dielectric properties suitable for this application.
14. The vertical transistor of claim 4 , wherein the horizontal air-gap height is from 4 nm to 20 nm and the horizontal air-gap width is from 30 nm to 50 nm.
A vertical transistor includes a fin or nanowire on a semiconductor substrate, a gate electrode around the fin/nanowire's sides, a bottom source/drain contact next to the gate, and a dielectric spacer between the gate and contact. The dielectric spacer has both a vertical air-gap and a horizontal air-gap. The horizontal air-gap's height ranges from 4 nm to 20 nm, and its width ranges from 30 nm to 50 nm. These dimensions are chosen to optimize the reduction of parasitic capacitance in the transistor.
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May 24, 2016
June 27, 2017
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