A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device comprising: a plurality of memory cells assigned with addresses that are different from each other; a redundant memory cell configured to replace a defective memory cell among the memory cells; a fuse circuit configured to store an address of the defective memory cell; an access control circuit configured to access the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied; a roll call circuit configured to output the address of the defective memory cell in a serial manner; and an input/output circuit configured to receive the address of the defective memory cell from the roll call circuit and to output the address of the defective memory cell to outside the semiconductor device via a data strobe terminal of the input/output circuit in the serial manner.
A semiconductor device contains multiple memory cells, each with a unique address. A redundant memory cell replaces any defective memory cell. A fuse circuit stores the address of the defective memory cell. An access control circuit uses this stored address to access the redundant memory cell instead of the defective one. A "roll call circuit" serially outputs the defective memory cell's address. An input/output circuit receives this serial address from the roll call circuit and transmits it outside the semiconductor device via a data strobe terminal, also in serial fashion.
2. The semiconductor device as claimed in claim 1 , wherein the roll call circuit includes a selection circuit configured to select, in the serial manner, a plurality of bits that constitute the address of the defective memory cell.
The semiconductor device, as described where a defective memory cell's address is serially output, the "roll call circuit" includes a selection circuit. This selection circuit serially chooses individual bits that make up the complete address of the defective memory cell.
3. The semiconductor device as claimed in claim 2 , wherein the selection circuit selects, in the serial manner, the plurality of bits by activating an exclusive selection signal for each bit of the plurality of bits.
In the semiconductor device featuring serial bit selection for the defective memory cell's address, the selection circuit serially selects each bit by activating a unique selection signal specifically for that bit. This ensures each bit of the address is individually accessed and outputted in sequence.
4. The semiconductor device as claimed in claim 2 , wherein the selection circuit is further configured to synchronize the selection of the plurality of bits with a test clock signal.
In the semiconductor device with serial bit selection of the defective memory cell's address, the selection circuit synchronizes the selection of these individual bits with a test clock signal. This synchronization ensures accurate and reliable serial output of the address bits.
5. A semiconductor device comprising: a plurality of memory cells assigned with addresses that are different from each other; a redundant memory cell configured to replace a defective memory cell among the memory cells; a fuse circuit configured to store an address of the defective memory cell; an access control circuit configured to access the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied: a roll call circuit configured to output the address of the defective memory cell in a serial manner, the address comprising a plurality of bits, wherein the roll call circuit includes: a plurality of first logic gate circuits, each of the first logic gate circuits configured to receive a corresponding one of the bits and a corresponding one of the selection signals; and a second logic gate circuit configured to perform logic synthesis of output signals of the plurality of first logic gate circuits; and an input/output circuit configured to receive the address of the defective memory cell from the roll call circuit and to output the address of the defective memory cell to outside the semiconductor device via a data strobe terminal of the input/output circuit in the serial manner.
A semiconductor device contains multiple memory cells, each with a unique address. A redundant memory cell replaces any defective memory cell. A fuse circuit stores the address of the defective memory cell. An access control circuit uses this stored address to access the redundant memory cell instead of the defective one. A "roll call circuit" serially outputs the defective memory cell's address, which comprises multiple bits. The roll call circuit contains multiple first logic gates that receive corresponding bits of the address and selection signals and a second logic gate to perform logic synthesis on the outputs of the first logic gates. An input/output circuit receives this serial address from the roll call circuit and transmits it outside the semiconductor device via a data strobe terminal, also in serial fashion.
6. The semiconductor device as claimed in claim 3 , wherein the selection circuit is configured to activate each exclusive selection signal in response to a test clock signal.
In the semiconductor device with serial bit selection using exclusive signals, as described where each bit of the defective memory cell address has its own selection signal, the selection circuit activates each of these exclusive selection signals in response to a test clock signal, ensuring synchronized bit selection.
7. The semiconductor device as claimed in claim 2 , wherein the fuse circuit includes a plurality of anti-fuse elements that are in a non-conductive state when not programmed and are in a conductive state when programmed.
In the semiconductor device, where a roll call circuit serially outputs the address of a defective memory cell, and the fuse circuit stores the address of the defective memory cell, the fuse circuit is comprised of multiple anti-fuse elements. These anti-fuses are initially non-conductive but become conductive when programmed, allowing them to store the defective memory cell address.
8. The semiconductor device as claimed in claim 7 , wherein the anti-fuse elements constitute a plurality of anti-fuse sets each configured to store an address of a corresponding defective memory cell, and the anti-fuse sets are selectively coupled to the roll call circuit based on a first selection signal.
In the semiconductor device where anti-fuses store the defective memory address, the anti-fuse elements are organized into multiple sets, each storing the address of a corresponding defective memory cell. These anti-fuse sets are selectively connected to the roll call circuit based on a first selection signal, enabling the roll call circuit to output the address of a specific defective memory cell.
9. The semiconductor device as claimed in claim 8 , wherein each of the plurality of anti-fuse sets includes two or more anti-fuse elements allocated to each of the bits.
In the semiconductor device using anti-fuse sets for storing defective memory addresses, each set contains two or more anti-fuse elements allocated to each bit of the address. This redundancy provides increased reliability for storing the address information.
10. The semiconductor device as claimed in claim 9 , wherein when the two or more anti-fuse elements all are in a non-conductive state, a corresponding bit is at a first logic level, and when at least one of the two or more anti-fuse elements is in a conductive state, a corresponding bit is at a second logic level.
In the semiconductor device employing redundant anti-fuses for each bit of the defective memory address, a bit is considered at a first logic level (e.g., 0) if all the anti-fuse elements for that bit are non-conductive. If at least one of the anti-fuse elements is conductive, the bit is considered at a second logic level (e.g., 1).
11. The semiconductor device as claimed in claim 10 , wherein the two or more anti-fuse elements are selectively coupled to the roll call circuit based on a second selection signal.
Building upon the anti-fuse implementation where two or more anti-fuses represent each bit of the defective address, these anti-fuse elements are selectively connected to the roll call circuit based on a second selection signal. This allows for selectively reading the stored address data from the anti-fuses.
12. The semiconductor device as claimed in claim 1 , wherein the fuse circuit includes a first storage circuit configured to store the address of the defective memory cell discovered in a wafer state, and a second storage circuit is configured to store the address of the defective memory cell discovered after packaging.
In the semiconductor device, where a roll call circuit serially outputs the address of a defective memory cell, the fuse circuit is made up of two storage circuits: the first stores the address of defective cells found during wafer testing, and the second stores the address of defective cells discovered after packaging. This allows for address storage at different manufacturing stages.
13. The semiconductor device as claimed in claim 12 , wherein the memory cells are respectively disposed at intersections of a plurality of word lines and a plurality of bit lines, and the second storage circuit is configured to store an address of a word line connected to the defective memory cell, among the word lines.
In the semiconductor device with two storage circuits (wafer-state and post-packaging), where a roll call circuit serially outputs the address of a defective memory cell, the memory cells are located at the intersections of word lines and bit lines. The second storage circuit, storing addresses found after packaging, specifically stores the address of the word line connected to the defective memory cell.
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August 27, 2014
July 11, 2017
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