The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
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1. A structure comprising: a first semiconductor fin adjacent to and parallel with a second semiconductor fin; a first gate structure perpendicular to and covering a middle portion of the first semiconductor fin; a second gate structure perpendicular to and covering a middle portion of the second semiconductor fin, wherein a width of the first gate structure is equal to a width of the second gate structure; a dielectric region in direct contact with and separating the first gate structure from the second gate structure; and a continuous spacer surrounding the first gate structure, the second gate structure, and the dielectric region, the continuous spacer is in direct contact with vertical sidewalls of each of the first gate structure, the second gate structure, and the dielectric region.
A semiconductor structure consists of two parallel semiconductor fins (first and second). A gate structure (first and second) crosses each fin perpendicularly at the middle, with equal widths. A dielectric material fills the space between the two gate structures. A spacer material surrounds both gate structures and the dielectric region, contacting their vertical sidewalls, thus forming a continuous layer. This structure is designed to minimize shorting between regions on the fins.
2. The structure of claim 1 , wherein the dielectric region comprises an oxide, a nitride, or an oxynitride.
The structure is implemented with two parallel semiconductor fins, first and second. A gate structure (first and second) crosses each fin perpendicularly at the middle, with equal widths. A dielectric material fills the space between the two gate structures. A spacer material surrounds both gate structures and the dielectric region, contacting their vertical sidewalls, thus forming a continuous layer. In this structure, the dielectric material separating the gate structures can be made of oxide, nitride, or oxynitride.
3. The structure of claim 1 , wherein both the first gate structure and the second gate structure comprise copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
This invention relates to semiconductor devices, specifically to gate structures in transistors. The problem addressed is the need for improved conductivity and reliability in gate materials to enhance device performance and longevity. Traditional gate materials like polysilicon or silicon-based alloys have limitations in conductivity and thermal stability, which can degrade performance in advanced semiconductor nodes. The invention describes a semiconductor device with a first gate structure and a second gate structure, where both structures are composed of highly conductive metals or alloys. These materials include copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or their alloys. The use of these metals improves electrical conductivity, reduces resistance, and enhances thermal stability compared to conventional gate materials. This leads to faster switching speeds, lower power consumption, and better reliability in integrated circuits. The invention is particularly useful in advanced logic and memory devices where high performance and durability are critical. The gate structures may be part of a transistor or other semiconductor component, ensuring efficient charge carrier movement and minimizing signal delays. The choice of metal or alloy can be tailored to specific applications, balancing conductivity, cost, and compatibility with manufacturing processes. This innovation addresses the growing demand for high-performance semiconductor devices in modern electronics.
4. The structure of claim 1 , wherein the first gate structure and the second gate structure both comprises polycrystalline silicon.
The structure is implemented with two parallel semiconductor fins, first and second. A gate structure (first and second) crosses each fin perpendicularly at the middle, with equal widths. A dielectric material fills the space between the two gate structures. A spacer material surrounds both gate structures and the dielectric region, contacting their vertical sidewalls, thus forming a continuous layer. In this structure, the gate structures are made of polycrystalline silicon.
5. The structure of claim 1 , wherein the width of both the first gate structure and the second gate structure is less than a width of the dielectric region.
The structure is implemented with two parallel semiconductor fins, first and second. A gate structure (first and second) crosses each fin perpendicularly at the middle, with equal widths. A dielectric material fills the space between the two gate structures. A spacer material surrounds both gate structures and the dielectric region, contacting their vertical sidewalls, thus forming a continuous layer. In this structure, the width of each gate structure is smaller than the width of the dielectric region separating them.
6. The structure of claim 1 , further comprising: a first epitaxial region on exposed portion of the first semiconductor fin; and a second epitaxial region on exposed portion of the second semiconductor fin, wherein the dielectric region isolates the first epitaxial region from the second epitaxial region.
The structure is implemented with two parallel semiconductor fins, first and second. A gate structure (first and second) crosses each fin perpendicularly at the middle, with equal widths. A dielectric material fills the space between the two gate structures. A spacer material surrounds both gate structures and the dielectric region, contacting their vertical sidewalls, thus forming a continuous layer. Furthermore, an epitaxial region is formed on the exposed part of each fin. The dielectric region isolates the epitaxial regions on the first fin from those on the second fin, preventing electrical shorts.
7. A structure comprising: a first set of fins adjacent to a second set of fins a first metal gate perpendicular to and covering a middle portion of the first set of fins; a second metal gate perpendicular to and covering a middle portion of the second set of fins, wherein a width of the first metal gate is equal to a width of the second metal gate; a dielectric region separating the first metal gate from the second metal gate, and wherein a top surface of the dielectric region is substantially flush with a top surface of each of the first set of fins and the second set of fins; a first source drain region above and in direct contact with an exposed portion of the first set of fins; a second source drain region above and in direct contact with an exposed portion of the second set of fins, wherein the dielectric region isolates the first source drain region from the second source drain region; and a continuous spacer surrounding the first metal gate, the second metal gate, and the dielectric region, the continuous spacer is in direct contact with vertical sidewalls of each of the first metal gate, the second metal gate, and the dielectric region.
A semiconductor structure includes two adjacent sets of fins. A metal gate structure crosses each set of fins perpendicularly at the middle, with equal widths. A dielectric material separates the two metal gate structures. The top surface of the dielectric is aligned with the top surface of the fins. Source/drain regions are formed on the exposed parts of the fins. The dielectric region isolates the source/drain regions of the first fin set from those of the second fin set. A spacer material surrounds both metal gate structures and the dielectric region, directly contacting their vertical sidewalls.
8. The structure of claim 7 , wherein the dielectric region comprises an oxide, a nitride, or an oxynitride.
The structure consists of two adjacent sets of fins. A metal gate structure crosses each set of fins perpendicularly at the middle, with equal widths. A dielectric material separates the two metal gate structures. The top surface of the dielectric is aligned with the top surface of the fins. Source/drain regions are formed on the exposed parts of the fins. The dielectric region isolates the source/drain regions of the first fin set from those of the second fin set. A spacer material surrounds both metal gate structures and the dielectric region, directly contacting their vertical sidewalls. The dielectric material separating the metal gate structures is made of oxide, nitride, or oxynitride.
9. The structure of claim 7 , wherein both the first metal gate and the second metal gate comprise copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
The structure consists of two adjacent sets of fins. A metal gate structure crosses each set of fins perpendicularly at the middle, with equal widths. A dielectric material separates the two metal gate structures. The top surface of the dielectric is aligned with the top surface of the fins. Source/drain regions are formed on the exposed parts of the fins. The dielectric region isolates the source/drain regions of the first fin set from those of the second fin set. A spacer material surrounds both metal gate structures and the dielectric region, directly contacting their vertical sidewalls. The metal gate structures are made of copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
10. The structure of claim 7 , wherein the first metal gate and the second metal gate both comprise polycrystalline silicon.
The structure consists of two adjacent sets of fins. A metal gate structure crosses each set of fins perpendicularly at the middle, with equal widths. A dielectric material separates the two metal gate structures. The top surface of the dielectric is aligned with the top surface of the fins. Source/drain regions are formed on the exposed parts of the fins. The dielectric region isolates the source/drain regions of the first fin set from those of the second fin set. A spacer material surrounds both metal gate structures and the dielectric region, directly contacting their vertical sidewalls. The metal gate structures are made of polycrystalline silicon.
11. The structure of claim 7 , wherein a width of both the first metal gate and the second metal gate is less than a width of the dielectric region.
The structure consists of two adjacent sets of fins. A metal gate structure crosses each set of fins perpendicularly at the middle, with equal widths. A dielectric material separates the two metal gate structures. The top surface of the dielectric is aligned with the top surface of the fins. Source/drain regions are formed on the exposed parts of the fins. The dielectric region isolates the source/drain regions of the first fin set from those of the second fin set. A spacer material surrounds both metal gate structures and the dielectric region, directly contacting their vertical sidewalls. The width of each metal gate structure is smaller than the width of the dielectric region separating them.
12. A structure comprising: a first fin group on a semiconductor substrate; a second fin group on the semiconductor substrate, the first fin group is separated from the second fin group by an intermediate region; a gate structure on a middle portion of the first fin group and a middle portion of the second fin group, the gate structure comprising a first metal gate and a second metal gate; a dielectric region in the intermediate region in direct contact with both the first metal gate and the second metal gate; one or more first epitaxial regions on the first fin group, the one or more first epitaxial regions are separated from each other by the first metal gate; one or more second epitaxial regions on the second fin group, the one or more second epitaxial regions separated from each other by the second metal gate, wherein the one or more first epitaxial regions are separated from the one or more second epitaxial regions by the dielectric region; and a continuous spacer surrounding the gate structure, and the dielectric region, the continuous spacer is in direct contact with vertical sidewalls of each of the gate structure and the dielectric region.
A semiconductor structure includes a first and second group of fins on a substrate separated by an intermediate region. A gate structure, comprising a first and second metal gate, sits on the middle of each fin group. A dielectric region resides in the intermediate region between the fin groups, contacting both metal gates. One or more epitaxial regions are on the first fin group, separated by the first metal gate. Similarly, one or more epitaxial regions are on the second fin group, separated by the second metal gate. The dielectric region separates the epitaxial regions of the first fin group from those of the second fin group. A continuous spacer surrounds the gate structure and dielectric region, contacting their vertical sidewalls.
13. The structure of claim 12 , wherein the dielectric region comprises an oxide, a nitride, or an oxynitride.
The structure includes a first and second group of fins on a substrate separated by an intermediate region. A gate structure, comprising a first and second metal gate, sits on the middle of each fin group. A dielectric region resides in the intermediate region between the fin groups, contacting both metal gates. One or more epitaxial regions are on the first fin group, separated by the first metal gate. Similarly, one or more epitaxial regions are on the second fin group, separated by the second metal gate. The dielectric region separates the epitaxial regions of the first fin group from those of the second fin group. A continuous spacer surrounds the gate structure and dielectric region, contacting their vertical sidewalls. The dielectric region comprises an oxide, a nitride, or an oxynitride.
14. The structure of claim 12 , wherein both the first metal gate and the second metal gate comprise copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
The structure includes a first and second group of fins on a substrate separated by an intermediate region. A gate structure, comprising a first and second metal gate, sits on the middle of each fin group. A dielectric region resides in the intermediate region between the fin groups, contacting both metal gates. One or more epitaxial regions are on the first fin group, separated by the first metal gate. Similarly, one or more epitaxial regions are on the second fin group, separated by the second metal gate. The dielectric region separates the epitaxial regions of the first fin group from those of the second fin group. A continuous spacer surrounds the gate structure and dielectric region, contacting their vertical sidewalls. The metal gates are made of copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
15. The structure of claim 12 , wherein the first metal gate and the second metal gate both comprise polycrystalline silicon.
The structure includes a first and second group of fins on a substrate separated by an intermediate region. A gate structure, comprising a first and second metal gate, sits on the middle of each fin group. A dielectric region resides in the intermediate region between the fin groups, contacting both metal gates. One or more epitaxial regions are on the first fin group, separated by the first metal gate. Similarly, one or more epitaxial regions are on the second fin group, separated by the second metal gate. The dielectric region separates the epitaxial regions of the first fin group from those of the second fin group. A continuous spacer surrounds the gate structure and dielectric region, contacting their vertical sidewalls. The metal gates are made of polycrystalline silicon.
16. The structure of claim 12 , wherein a width of both the first metal gate and the second metal gate is less than a width of the dielectric region.
The structure includes a first and second group of fins on a substrate separated by an intermediate region. A gate structure, comprising a first and second metal gate, sits on the middle of each fin group. A dielectric region resides in the intermediate region between the fin groups, contacting both metal gates. One or more epitaxial regions are on the first fin group, separated by the first metal gate. Similarly, one or more epitaxial regions are on the second fin group, separated by the second metal gate. The dielectric region separates the epitaxial regions of the first fin group from those of the second fin group. A continuous spacer surrounds the gate structure and dielectric region, contacting their vertical sidewalls. The width of each metal gate is smaller than the width of the dielectric region.
17. The structure of claim 12 , wherein the dielectric region is above and in direct contact with the semiconductor substrate.
The structure includes a first and second group of fins on a substrate separated by an intermediate region. A gate structure, comprising a first and second metal gate, sits on the middle of each fin group. A dielectric region resides in the intermediate region between the fin groups, contacting both metal gates. One or more epitaxial regions are on the first fin group, separated by the first metal gate. Similarly, one or more epitaxial regions are on the second fin group, separated by the second metal gate. The dielectric region separates the epitaxial regions of the first fin group from those of the second fin group. A continuous spacer surrounds the gate structure and dielectric region, contacting their vertical sidewalls. The dielectric region sits directly on the semiconductor substrate.
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July 7, 2016
July 11, 2017
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