Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A compiling apparatus comprising: an analysis unit configured to generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes, to determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and to add information about the determined data width of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and a data processing unit configured to provide instructions to be executed by a processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph, wherein the type information comprises a value indicating a number of bits, and the data processing unit is further configured to select, in response to respective determinations of the determined data widths of the operands and the connections in the data flow graph, instructions comprising a data width matching the determined data widths of the operands and the connections in the data flow graph, and wherein the analysis unit is further configured to initialize data widths of input and output nodes in the data flow graph based on the type information of the operands and to determine and set, using a fixed-point algorithm, data widths of unknown operands and connections as minimal data widths thereof from among available data widths.
A compiler takes source code and creates instructions for a heterogeneous processor (a processor with components that handle different data widths). The compiler analyzes the code to build a data flow graph, where nodes are inputs, operations, and outputs, and connections show how data flows. It determines the data widths (e.g., number of bits) of operands and connections using type information from the source code. It then selects processor instructions that match these data widths. Initially, it sets data widths for known input and output nodes. For unknown data widths, it uses a fixed-point algorithm to find the smallest possible data widths from the available options. The compiler stores these widths within the data flow graph for later use.
2. The compiling apparatus of claim 1 , wherein the heterogeneous components comprise at least one functional unit that processes data having a respective data width, register files that store data having different data widths, and connecting wires suitable for different data widths.
This system compiles code for computer chips that use different sized data units (like bytes, words, etc.), different sized storage areas for that data, and different sized connections between them. So basically, it handles a variety of data sizes.
3. The compiling apparatus of claim 1 , wherein the data processing unit is further configured to determine functional units to execute the selected instructions.
The compiler for heterogeneous processors, as described previously, not only selects the correct instructions based on data width, but it also determines which functional units in the heterogeneous processor should execute those instructions. This allows it to map operations to the most suitable hardware unit, considering factors like data width support and available resources, to improve overall processing efficiency and performance of the heterogeneous processor.
4. The compiling apparatus of claim 1 , wherein the data processing unit is further configured to allocate registers based on the determined data widths of the operands and the connections in the data flow graph.
The compiler for heterogeneous processors, as described previously, allocates registers in the heterogeneous processor based on the data widths determined during data flow graph analysis. This register allocation step ensures that operands are stored in registers that are large enough to hold the data, preventing data overflow. By considering data widths during register allocation, the compiler avoids wasting register space and optimizes memory usage within the heterogeneous processor.
5. The compiling apparatus of claim 1 , wherein if the processor is a coarse grained array (CGA) processor, the data processing unit is further configured to determine data widths of input and output operands and connections of nodes existing on the CGA processor's routing paths, which are used for execution of the selected instructions, based on the determined data widths of the operands and the connections in the data flow graph.
For heterogeneous processors that are coarse-grained arrays (CGAs), the compiler, as described previously, further refines its analysis. After instruction selection, it determines the data widths needed for the CGA processor's routing paths used to execute the selected instructions. This means it looks at the data widths required for inputs, outputs, and connections of nodes along the specific paths the data will take on the CGA processor, based on the data widths in the initial data flow graph.
6. The compiling apparatus of claim 5 , wherein the processor is a very long instruction word (VLIW) processor or a CGA processor.
The compiler for heterogeneous processors using CGA architecture, as described previously, supports two processor types: Very Long Instruction Word (VLIW) processors and Coarse Grained Array (CGA) processors. The method is tailored to optimize code for either of these processor architectures, where the data width considerations are important for efficient execution.
7. A compiling method of a compiling apparatus, the compiling method comprising: generating, by an analysis unit, a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes; determining data widths of input and output operands of the nodes and the connections in the data flow graph using type information of the operands; adding information about the determined data width of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and providing, by a data processing unit of the compiling apparatus, instructions to be executed by a heterogeneous processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph, wherein the type information comprises a value indicating a number of bits, and the providing of the instructions further comprises selecting, in response to respective determinations of the determined data widths of the operands and the connections in the data flow graph, instructions comprising a data width matching the determined data widths of the operands and the connections in the data flow graph, and wherein the determining of the respective data widths of the operands and the connections in the data flow graph comprises: initializing data widths of input and output nodes in the data flow graph based on the type information of the operands; and determining and setting, using a fixed point algorithm, data widths of unknown operands and connections as minimal data widths thereof from among available data widths.
A compiler method involves generating a data flow graph representing the code, where nodes are inputs, operations, and outputs, and connections represent data flow. It determines the data widths (number of bits) of operands and connections using type information. This information is stored in the data flow graph. The compiler then provides instructions for a heterogeneous processor based on these data widths. This involves selecting instructions with data widths that match the determined operand and connection widths. Initially, input and output nodes have their data widths initialized based on type information. Unknown data widths are determined using a fixed-point algorithm to find the minimal necessary widths from the available options.
8. The compiling method of claim 7 , wherein the heterogeneous components comprise at least one functional unit that processes data having a respective data width, register files that store data having different data widths, and connecting wires suitable for different data widths.
The compiling method for heterogeneous processors, as described previously, targets processors with heterogeneous components: functional units that process data of specific widths, register files that store data of different sizes, and connecting wires designed for varying data widths. The method leverages these hardware differences to optimize code execution based on the determined data widths.
9. The compiling method of claim 7 , wherein the providing of the instructions further comprises determining functional units to execute the selected instructions.
The compiling method for heterogeneous processors, as described previously, selects instructions based on data width and also determines which functional units within the heterogeneous processor should execute those instructions. This unit selection optimizes performance by mapping operations to the most appropriate hardware resources.
10. The compiling method of claim 7 , wherein the providing of the instructions further comprises allocating registers based on the determined data widths of the operands and the connections in the data flow graph.
The compiling method for heterogeneous processors, as described previously, also allocates registers in the target processor based on the determined data widths. This allocation ensures that the data can be stored without overflow and optimizes register usage.
11. The compiling method of claim 7 , wherein the providing of the instructions comprises, if the processor is a coarse grained array (CGA) processor, determining data widths of input and output operands and connections of nodes existing on the CGA processor's routing paths, which are used for execution of the selected instructions, based on the determined data widths of the operands and the connections in the data flow graph.
The compiling method, as described previously, for a Coarse Grained Array (CGA) processor refines data width analysis further. After instruction selection, it determines the data widths needed for the input and output operands and connections of nodes specifically along the routing paths used by the CGA to execute the selected instructions, based on the initial data flow graph.
12. The compiling method of claim 7 , wherein the heterogeneous processor is a very long instruction word (VLIW) processor or a CGA processor.
The compiling method, as described previously, targets either a Very Long Instruction Word (VLIW) processor or a Coarse Grained Array (CGA) processor. The compiling process is designed to generate optimized instructions based on data widths for either of these processor types.
13. A compiling apparatus comprising: a processor configured to generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes, determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and add, to the data flow graph, information about the determined data widths of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and provide instructions, to be executed by a processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph, select, in response to the determining of the data widths of the operands and the connections in the data flow graph, instructions comprising an operand data width corresponding to the determined data widths of the operands and the connections in the data flow graph, and use initial data widths of operands and connections, determined using the type information, to determine unknown minimal data widths of operands and connections through an iterative process that repeats until the determined unknown data widths of operands and connections do not change.
A compiler apparatus creates a data flow graph from source code, representing inputs, operations, and outputs as nodes connected by data flows. It determines the data widths of operands and connections using type information. The data flow graph is then augmented with this data width information. Next, the compiler selects instructions for a heterogeneous processor, where instruction selection is based on matching the instruction's operand data width with the determined data widths in the data flow graph. The compiler uses type information to initialize data widths. It refines unknown data widths using an iterative fixed-point algorithm that converges to the minimal data widths for operands and connections.
14. The apparatus of claim 13 , further comprising a memory configured to store instructions, wherein the processor is further configured to execute the instructions to configure the processor to: generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes, to determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and to add, to the data flow graph, information about the determined data widths of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and a data processing unit configured to provide instructions, to be executed by a processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph, wherein the data processing unit is further configured to select, in response to respective determinations of the determined the determining of the data widths of the operands and the connections in the data flow graph, instructions comprising an operand data width corresponding to the determined data widths of the operands and the connections in the data flow graph, and use initial data widths of operands and connections, determined using the type information, to determine unknown minimal data widths of operands and connections through an iterative process that repeats until the determined unknown data widths of operands and connections do not change.
A compiler apparatus, as described previously, incorporates a memory to store instructions. The processor is programmed to execute these instructions, which guide the creation of a data flow graph. The data flow graph depicts inputs, operations, and outputs as nodes with connecting data flows. The processor determines the data widths of operands and connections using type information and adds this information to the graph. Then, instructions are selected for a heterogeneous processor such that the instruction's operand data width is matched to the data widths in the data flow graph. An iterative process utilizing initial data widths from type information is employed to determine the minimum data widths for operands and connections, ensuring optimal hardware usage.
15. The apparatus of claim 13 wherein the processor comprises a data processing unit configured to determine a routing path for delivering a result of a first operation node to a second operation node, the routing path comprising register nodes having a data width greater than or equal to a data width of the result of the first operation node to be delivered to the second operation node.
In the compiler apparatus, as described previously, the processor includes a data processing unit that determines routing paths for data transfer. When moving data from a first operation to a second operation, the routing path will include register nodes that are large enough to hold the data. Register node data widths must be equal to or greater than the data being transferred.
16. The apparatus of claim 13 wherein the heterogeneous components comprise: a 32-bit functional unit which receives data having a data width up to 32 bits; and a 64-bit functional unit which receives data having a data width up to 64 bits.
In the compiler apparatus, as described previously, the heterogeneous components of the processor include functional units of different data widths. Specifically, it might include a 32-bit functional unit capable of receiving data up to 32 bits wide, and a 64-bit functional unit capable of receiving data up to 64 bits wide. This allows for efficient processing of different data types and sizes.
17. The apparatus of claim 13 wherein a result of an upstream node of the data flow graph is delivered as an input to a downstream node of the data flow graph, and a result of the downstream node is delivered as an input to the upstream node.
In the compiler apparatus, as described previously, a data flow graph can have feedback loops. The output of an upstream node can be used as input to a downstream node, and the output of that downstream node is used as input to the upstream node.
18. The apparatus of claim 13 wherein a result of a first operation node of the data flow graph is delivered to a second operation node of the data flow graph, and the second operation node comprises a data width different from a data width of the first operation node.
In the compiler apparatus, as described previously, data widths can change during the data flow. The output of a first operation node can be passed to a second operation node, where the data width of the second node is different than the data width of the first node. This supports cases where data needs to be converted to different sizes during processing.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 22, 2009
July 18, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.