Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.
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1. A method of fabricating a III-V semiconductor device, the method comprising the steps of: providing a substrate having an indium phosphide-ready layer; forming an iron-doped indium phosphide layer on the indium phosphide-ready layer; forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device.
A method for building a III-V semiconductor device involves these steps: Start with a substrate prepared with an indium phosphide (InP)-ready layer. Deposit a layer of iron (Fe)-doped InP on top of this InP-ready layer. Grow an epitaxial layer of III-V semiconductor material on the Fe-doped InP. Pattern the epitaxial layer to create the active device areas, specifically creating mesa structures which form the active areas. This structure uses the Fe-doped InP layer for device isolation.
2. The method of claim 1 , wherein the iron-doped indium phosphide layer has a resistivity of greater than 1E5 Ω·cm.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device, wherein the iron-doped indium phosphide layer has a high resistivity, specifically greater than 1E5 Ω·cm. This high resistivity helps improve device isolation.
3. The method of claim 1 , wherein the epitaxial III-V semiconductor material layer comprises indium gallium arsenide with an indium composition configured to lattice match the indium gallium arsenide to a lattice constant of indium phosphide.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device, wherein the epitaxial III-V semiconductor material is indium gallium arsenide (InGaAs). The composition of the InGaAs is adjusted to match the lattice constant of indium phosphide (InP) for optimal crystal growth.
4. The method of claim 1 , further comprising the steps of: forming a buffer layer on the iron-doped indium phosphide layer such that the buffer layer is present between the iron-doped indium phosphide layer and the epitaxial III-V semiconductor material layer; and patterning the epitaxial III-V semiconductor material layer and the buffer layer to form the one or more active areas of the device.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device, which further comprises forming a buffer layer between the iron-doped InP layer and the epitaxial III-V semiconductor layer. Both the epitaxial III-V layer and the buffer layer are patterned to form the active device areas.
5. The method of claim 4 , wherein the buffer layer comprises indium aluminum arsenide or intrinsic indium phosphide.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device forming a buffer layer on the iron-doped indium phosphide layer such that the buffer layer is present between the iron-doped indium phosphide layer and the epitaxial III-V semiconductor material layer, and patterning the epitaxial III-V semiconductor material layer and the buffer layer to form the one or more active areas of the device, wherein the buffer layer is made of either indium aluminum arsenide (InAlAs) or intrinsic indium phosphide (InP).
6. The method of claim 4 , further comprising the step of: oxidizing the buffer layer to convert the buffer layer to an insulator.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device forming a buffer layer on the iron-doped indium phosphide layer such that the buffer layer is present between the iron-doped indium phosphide layer and the epitaxial III-V semiconductor material layer, and patterning the epitaxial III-V semiconductor material layer and the buffer layer to form the one or more active areas of the device, which further comprises oxidizing the buffer layer after it is formed and patterned. This oxidation turns the buffer layer into an insulating material, further enhancing device isolation.
7. The method of claim 6 , wherein the buffer layer is indium aluminum arsenide which is converted via the oxidizing into an aluminum oxide insulator.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device forming a buffer layer on the iron-doped indium phosphide layer such that the buffer layer is present between the iron-doped indium phosphide layer and the epitaxial III-V semiconductor material layer, and patterning the epitaxial III-V semiconductor material layer and the buffer layer to form the one or more active areas of the device, and oxidizing the buffer layer to convert the buffer layer to an insulator, wherein the buffer layer is indium aluminum arsenide (InAlAs). Oxidizing the InAlAs converts it into aluminum oxide (AlOx), which acts as an insulator.
8. The method of claim 6 , wherein the oxidizing of the buffer layer is selective with respect to the iron-doped indium phosphide layer and the epitaxial III-V semiconductor material layer.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device forming a buffer layer on the iron-doped indium phosphide layer such that the buffer layer is present between the iron-doped indium phosphide layer and the epitaxial III-V semiconductor material layer, and patterning the epitaxial III-V semiconductor material layer and the buffer layer to form the one or more active areas of the device, and oxidizing the buffer layer to convert the buffer layer to an insulator, where the oxidation process is selective. This means that the oxidation primarily affects the buffer layer and does not significantly oxidize the iron-doped InP layer or the epitaxial III-V semiconductor material layer.
9. The method of claim 1 , wherein the substrate comprises a graded III-V buffer layer on a silicon substrate, wherein a portion of the graded III-V buffer layer is the indium phosphide-ready layer, and wherein the indium phosphide-ready layer comprises indium phosphide, indium gallium arsenide, or indium aluminum arsenide.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device, wherein the base substrate is silicon, and a graded III-V buffer layer is grown on the silicon substrate to transition to an indium phosphide-ready layer. The InP-ready layer can be made of InP, indium gallium arsenide (InGaAs), or indium aluminum arsenide (InAlAs).
10. The method of claim 1 , wherein the epitaxial III-V semiconductor material layer comprises a material selected from the group consisting of aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium nitride, indium nitride, indium phosphide, indium gallium arsenide phosphide and combinations comprising at least one of the foregoing materials.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device, wherein the epitaxial III-V semiconductor layer is selected from a group of III-V materials. This group includes aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium nitride, indium nitride, indium phosphide, indium gallium arsenide phosphide, and combinations thereof.
11. The method of claim 1 , wherein the epitaxial III-V semiconductor material layer comprises indium gallium arsenide.
The method of fabricating a III-V semiconductor device comprises providing a substrate having an indium phosphide-ready layer, forming an iron-doped indium phosphide layer on the indium phosphide-ready layer, forming an epitaxial III-V semiconductor material layer on the iron-doped indium phosphide layer, and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is patterned to form one or more mesas which comprise the one or more active areas of the device, wherein the epitaxial III-V semiconductor material layer is specifically indium gallium arsenide (InGaAs).
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March 21, 2016
July 25, 2017
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