Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising a semiconductor chip, the semiconductor chip comprising: a first conductive via penetrating a semiconductor substrate that has a first main surface and a second main surface thereof and including a first end on a side of the first main surface and a second end on a side of the second main surface, the first conductive via being configured to receive a first signal at the first end, and further being configured to provide a second signal from the second end; and a second conductive via penetrating the semiconductor substrate and including a third end on the side of the first main surface and a fourth end on the side of the second main surface, the second conductive via being configured to provide a third signal from the third end, and further configured to receive a fourth signal corresponding to the second signal at the fourth end.
A semiconductor chip includes a first conductive via that passes through the chip's substrate. This via receives an input signal at one end and outputs a signal at the opposite end. A second conductive via also penetrates the substrate. It receives a signal corresponding to the output of the first via at one end, and outputs a signal at the other end. Essentially, two vias are connected in series through the substrate to transmit a signal.
2. The apparatus as claimed in claim 1 , further comprising: a delay circuit configured to delay the first signal and further configured to provide a first delayed signal; and a latch circuit configured to latch the third signal responsive to the first delayed signal.
The semiconductor chip described above (two conductive vias passing through the substrate, with the first via's output connected to the second via's input) also includes a delay circuit that delays the initial input signal and outputs a delayed version. A latch circuit captures the output signal from the second via based on the timing of the delayed input signal. This allows for analyzing timing characteristics through the vias.
3. The apparatus as claimed in claim 1 , further comprising: a first delay circuit configured to delay the first signal and further configured to provide a first delayed signal; a first latch circuit configured to latch the third signal responsive to the first delayed signal; a second delay circuit configured to delay the first signal and further configured to provide a second delayed signal; a second latch circuit configured to latch the third signal responsive to the second delayed signal; and a logic circuit configured to produce a monitor signal responsive to output signals of the first and second latch circuits.
The semiconductor chip described above (two conductive vias passing through the substrate, with the first via's output connected to the second via's input) has a more complex analysis circuit. It contains a first delay circuit that delays the initial input signal and outputs a first delayed version; a first latch circuit that captures the output signal from the second via based on the timing of the first delayed input signal. It also has a second delay circuit that delays the initial input signal by a *different* amount and outputs a second delayed version; a second latch circuit that captures the output of the second via based on the timing of *this* delayed input signal. Finally, a logic circuit compares the outputs of the two latch circuits to create a monitor signal indicating signal delay.
4. The apparatus as claimed in claim 1 , further comprising; a divider configured to provide a divided clock signal responsive to the first signal; and a third conductive via penetrating the semiconductor substrate and configured to receive the divided clock signal.
The semiconductor chip described above (two conductive vias passing through the substrate, with the first via's output connected to the second via's input) also contains a divider circuit that reduces the frequency of the initial input signal and outputs a divided clock signal. A third conductive via penetrates the substrate to receive this lower-frequency clock signal. This allows testing signal integrity at different frequencies.
5. The apparatus of claim 4 , further comprising: a fourth conductive via penetrating the semiconductor substrate and configured to receive the divided clock signal from the third conductive via at one end and provide the divided clock signal at another end responsive to the received divided clock signal at the one end; and a latch circuit configured to latch the divided clock signal for reception by the third signal.
The semiconductor chip described above (with two conductive vias passing through the substrate, a divider creating a divided clock, and a third via carrying the divided clock) also includes a *fourth* conductive via. This fourth via receives the divided clock signal from the third via at one end, and outputs it at the other. A latch circuit captures the divided clock signal based on the output signal from the *second* conductive via. This allows comparing the signal delays between different vias and the clock divider.
6. The apparatus of claim 1 , further comprising a time adjustment circuit configured to receive the first signal and the evaluation result signal, and further configured to provide an adjustment clock signal.
The semiconductor chip described above (two conductive vias passing through the substrate, with the first via's output connected to the second via's input) also includes a time adjustment circuit. This circuit receives the initial input signal AND an "evaluation result signal" (which indicates the frequency of the input signal based on the delay through the vias). The time adjustment circuit then outputs an "adjustment clock signal", presumably adjusted to compensate for delays or signal degradation detected by the evaluation circuit.
7. The apparatus as claimed in claim 1 , further comprising: a first circuit configured to produce a control signal responsive to the third signal; a first terminal configured to receive a data signal; a logic circuit configured to adjust a duty cycle of the data signal responsive to the control signal.
The semiconductor chip described above (two conductive vias passing through the substrate, with the first via's output connected to the second via's input) contains a circuit that creates a "control signal" based on the output of the *second* via. It also includes a terminal to receive a data signal. Finally, a logic circuit adjusts the "duty cycle" (on/off ratio) of this data signal based on the control signal derived from the via output. This implies the vias are being used to dynamically adjust data transmission characteristics.
8. An apparatus comprising: a controller configured to provide a clock signal as a first signal; a first conductive via configured provide a second signal responsive to the first signal; a second conductive via coupled to the first conductive via and configured to provide a third signal responsive to the second signal; and an evaluation circuit configured to provide an evaluation result signal responsive to the third signal, wherein the evaluation result signal is indicative of a frequency of the clock signal and is based on a delay of the third signal relative to the clock signal.
A system monitors signal delay using conductive vias. A controller provides a clock signal. A first via transmits this signal, producing a slightly delayed version. A second via, connected to the first, further transmits and delays the signal. An evaluation circuit analyzes the final signal and outputs a result indicating the original clock signal's frequency, based on the overall signal delay caused by the vias.
9. The apparatus of claim 8 , further comprising an interface die, wherein the interface die includes the first conductive via, the second conductive via and the evaluation circuit.
The system that monitors signal delay through conductive vias (clock signal source, two vias in series, and an evaluation circuit determining frequency based on delay) has the first via, the second via, and evaluation circuit integrated into a single "interface die". This concentrates the delay measurement components.
10. The apparatus of claim 8 , wherein an evaluation circuit comprises: a delay circuit configured to receive the first signal and to delay the first signal based on a propagation delay related to effective capacitance of the first conductive via with a first threshold frequency, the delay circuit further configured to provide a first delayed signal; and a latch circuit configured to latch the third signal responsive to the first delayed signal.
The system for monitoring signal delay using conductive vias (clock signal source, two vias in series, and an evaluation circuit determining frequency based on delay) determines the frequency by: using a delay circuit to delay the *initial* clock signal. The delay amount is related to the capacitance of the *first* via and a defined threshold frequency. A latch circuit then captures the *second* via's output based on the timing of this delayed clock signal. The latch state indicates whether the frequency is above or below the threshold.
11. The apparatus of claim 8 , wherein the evaluation circuit comprises: a first comparator configured to detect whether a frequency of the first signal is below a first threshold frequency, and further configured to provide a first evaluation result signal; a second comparator configured to detect whether the frequency of the first signal is above a second threshold frequency that is higher than the first threshold frequency, and further configured to provide a second evaluation result signal; and a logic circuit configured to receive the first evaluation result signal and the second evaluation result signal, and further configured to provide a signal indicative of whether the frequency of the first signal is in a low frequency region below the first threshold frequency, in a middle frequency region between the first threshold frequency and the second threshold frequency or in a high frequency region above the second threshold frequency.
The system for monitoring signal delay using conductive vias (clock signal source, two vias in series, and an evaluation circuit determining frequency based on delay) determines frequency using two comparators and logic. The first comparator checks if the frequency is *below* a first threshold. The second checks if it's *above* a second, higher threshold. The logic circuit then outputs a signal indicating whether the frequency is "low" (below the first threshold), "medium" (between the thresholds), or "high" (above the second threshold).
12. The apparatus of claim 11 , wherein the first comparator comprises: a first delay circuit configured to delay the first signal based on a first propagation delay related to effective capacitance of the first conductive via with a first threshold frequency, and further configured to provide a first delayed signal; and a first latch circuit configured to latch the third signal responsive to the first delayed signal, and wherein the second comparator comprises: a second delay circuit configured to delay the first signal based on a second propagation delay related to effective capacitance of the first conductive via with a second threshold frequency, and further configured to provide a second delayed signal; and a second latch circuit configured to latch the third signal responsive to the second delayed signal.
In the system that monitors signal delay using conductive vias and determines frequency bands (low, medium, high) via comparators, the first comparator (for detecting frequencies below a threshold) uses a delay circuit to delay the initial signal based on a propagation delay of the first via related to the first frequency threshold, and a latch circuit to capture the second via’s output. The second comparator (for detecting frequencies above a higher threshold) works similarly, but uses a *different* delay circuit that is based on a propagation delay related to the *second* threshold, along with its own latch.
13. The apparatus of claim 8 , wherein the evaluation circuit further comprises a divider configured to provide a divided clock signal responsive to the first signal, and the apparatus further comprises: a third conductive via configured to receive the divided clock signal, wherein the evaluation circuit is configured to provide the evaluation result signal based on the divided clock signal and the third signal.
The system for monitoring signal delay using conductive vias (clock signal source, two vias in series, and an evaluation circuit determining frequency based on delay) also uses a frequency divider to create a lower-frequency clock signal from the initial clock. A third conductive via then transmits this divided clock signal. The evaluation circuit uses *both* the divided clock signal and the output of the second via to determine the result signal.
14. The apparatus of claim 13 , further comprising: a fourth conductive via configured to receive a signal from the third conductive via and further configured to provide the divided clock signal, wherein the evaluation circuit further including a latch circuit configured to latch the divided clock signal responsive to the third signal and the divided clock signal.
The system that monitors signal delay using conductive vias and includes a divided clock signal transmitted via a third via, also has a *fourth* via. This fourth via receives the divided clock signal from the third and re-transmits it. The evaluation circuit uses a latch to capture the divided clock signal based on the timing of the second via's output, to refine the delay measurement.
15. The apparatus of claim 8 , further comprising: a time adjustment circuit configured to receive the first signal and the evaluation result signal, and further configured to provide an adjustment clock signal.
The system that monitors signal delay through conductive vias (clock signal source, two vias in series, and an evaluation circuit determining frequency based on delay) also contains a time adjustment circuit. This circuit receives the initial clock signal AND the evaluation result signal. It then outputs an adjusted clock signal based on this information, likely to compensate for the detected delays.
16. The apparatus of claim 8 , further comprising: a first terminal configured to receive a data signal from the controller; a variable data transfer rate circuit configured to receive the evaluation result signal and further configured to adjust a duty cycle of the data signal responsive to the evaluation result signal.
The system that monitors signal delay through conductive vias (clock signal source, two vias in series, and an evaluation circuit determining frequency based on delay) also includes a data signal input and a "variable data transfer rate circuit". This circuit receives the evaluation result signal (frequency indication) and adjusts the "duty cycle" (on/off ratio) of the *data* signal accordingly. This allows for dynamic data rate control based on signal integrity.
17. The apparatus of claim 16 , wherein the evaluation circuit is configured to provide the evaluation result signal responsive to the third signal by detecting whether a frequency of the third signal is higher than a second threshold frequency.
In the system with variable data transfer rates that adjusts the data duty cycle based on the evaluation of the via signal, the evaluation circuit determines frequency by detecting if the *second* via's output signal's frequency is *higher* than a threshold frequency. This single threshold detection influences the data transfer rate.
18. The apparatus of claim 16 , further comprising a pulse generator, wherein the controller includes a clock generator configured to provide the clock signal, and wherein the pulse generator is configured to provide a transmitter clock signal to the first conductive via and the variable data transfer rate circuit is responsive to the clock signal.
The system with variable data transfer rates that adjusts the data duty cycle based on the evaluation of the via signal also incorporates a pulse generator. The system's controller contains a clock generator to create the main clock signal. The pulse generator sends a "transmitter clock signal" to *both* the first conductive via AND the variable data transfer rate circuit. This coordinates the via signal testing with the data transmission.
19. An apparatus comprising: a controller configured to provide a clock signal; an interface die comprising: a first conductive via configured to receive the clock signal as a first signal and further configured to provide a second signal; a divider configured to provide a divided clock signal responsive to the first signal; and a second conductive via configured to receive the divided clock signal and further configured to provide a divided clock signal; and a core die comprising: an evaluation circuit configured to provide an evaluation result signal responsive to the divided clock signal and the second signal.
A system consists of a controller providing a clock signal, an interface die, and a core die. The interface die includes a first via receiving the clock signal and outputting another signal, a divider generating a divided clock signal from the first signal, and a second via receiving and outputting the divided clock signal. The core die includes an evaluation circuit. This evaluation circuit provides a result signal in response to the divided clock signal and the second signal. This setup segregates the high-speed interface components onto one die, and the processing on another.
20. The apparatus of claim 19 wherein the evaluation circuit comprises a latch circuit configured to latch the divided clock signal for reception responsive to the second signal.
In the system with separate interface and core dies, and a divided clock signal being evaluated along with via signals, the evaluation circuit contains a latch. This latch captures the divided clock signal based on the timing of the second signal, facilitating a precise comparison of arrival times and thus an accurate delay measurement.
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April 25, 2016
August 1, 2017
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