A method for fabricating a test structure on a wafer includes forming a fin on a substrate, forming a first gate stack over the fin, the first gate stack having a first gate width, the first gate stack including a gate dielectric layer having a first thickness, forming a second gate stack over the fin, the second gate stack having a second gate width, the second gate stack including a gate dielectric layer having a second thickness, and forming a third gate stack over the fin, the third gate stack having a third gate width, the third gate stack including a gate dielectric layer having the second thickness, wherein the first gate stack is arranged a first distance from the second gate stack and the second gate stack is arranged the first distance from the third gate stack.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for fabricating a test structure on a wafer, the method comprising: forming a semiconductor fin on a substrate; forming a first dummy gate stack over the fin, the first dummy gate stack having a first width; forming a second dummy gate stack over the fin, the second dummy gate stack having a second width; forming a third dummy gate stack over the fin, the third dummy gate stack having a third width, the first dummy gate stack is spaced a first distance from the second dummy gate stack, the second dummy gate stack spaced the first distance from the third dummy gate stack; forming a source/drain regions on exposed portions of the fin; removing the first dummy gate, the second dummy gate, and the third dummy gate to expose channel regions of the fin; depositing a layer of dielectric material over the channel regions of the fin; depositing a block mask to obscure a channel region of the fin, the block mask formed on a first portion but not a second portion of a top surface of the layer of dielectric material; removing the layer of dielectric material from exposed channel regions of the fin; removing the block mask; depositing a high-k dielectric layer; and depositing a work function metal to form a first gate stack, a second gate stack, and a third gate stack.
A method for creating a test structure on a wafer involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form the final first, second, and third gate stacks.
2. The method of claim 1 , further comprising forming spacers adjacent to the first dummy gate stack, the second dummy gate stack and the third dummy gate stack prior to forming the source/drain regions.
The method described above for creating a test structure on a wafer, further includes creating spacers around the three temporary "dummy" gate stacks (first, second, and third) *before* creating the source/drain regions. This involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) forming spacers adjacent to the first dummy gate stack, the second dummy gate stack and the third dummy gate stack; 5) creating source/drain regions on the exposed parts of the fin; 6) removing the dummy gates, revealing the fin's channel regions; 7) coating the channel regions with a dielectric material; 8) using a mask to cover part of the dielectric layer; 9) removing the exposed dielectric material; 10) removing the mask; and 11) depositing a high-k dielectric and a metal layer to form the final first, second, and third gate stacks.
3. The method of claim 1 , wherein the forming the source/drain regions on exposed portions of the fin includes epitaxially growing a semiconductor material on exposed portions of the fin.
In the method for creating a test structure on a wafer, the step of creating source/drain regions on the exposed parts of the fin involves growing a semiconductor material (epitaxially) on these exposed regions. This means: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin by growing a semiconductor material on exposed portions of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form the final first, second, and third gate stacks.
4. The method of claim 1 , wherein the first width is greater than the second width.
In the method for creating a test structure on a wafer, the first temporary "dummy" gate stack has a greater width than the second temporary "dummy" gate stack. This involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width, where the first dummy gate has a greater width than the second dummy gate; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form the final first, second, and third gate stacks.
5. The method of claim 1 , wherein the second width is greater than the third width.
In the method for creating a test structure on a wafer, the second temporary "dummy" gate stack has a greater width than the third temporary "dummy" gate stack. This means: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width, where the second dummy gate has a greater width than the third dummy gate; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form the final first, second, and third gate stacks.
6. The method of claim 1 , wherein the first gate stack includes the layer of dielectric material and the high-k dielectric layer, and the second gate stack includes the high-k dielectric layer.
In the method for creating a test structure on a wafer, the first final gate stack is made from the original dielectric material *and* the high-k dielectric layer, while the second final gate stack is made *only* from the high-k dielectric layer. This involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form a first gate stack (made from the original dielectric and high-k dielectric), a second gate stack (made only from the high-k dielectric layer), and a third gate stack.
7. The method of claim 1 , wherein the third gate stack includes the high-k dielectric layer and the layer of dielectric material.
In the method for creating a test structure on a wafer, the third final gate stack is made from the high-k dielectric layer *and* the original dielectric material. This involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form a first gate stack, a second gate stack, and a third gate stack (made from the high-k dielectric layer and the original dielectric material).
8. The method of claim 1 , wherein the layer of dielectric material includes a low-k dielectric material.
In the method for creating a test structure on a wafer, the original dielectric material used to coat the channel regions is a "low-k" dielectric material. This involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) creating source/drain regions on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a low-k dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form a first gate stack, a second gate stack, and a third gate stack.
9. The method of claim 1 , wherein the source/drain regions, are substantially the same size and shape.
In the method for creating a test structure on a wafer, the source/drain regions created on the fin are substantially the same size and shape. This involves: 1) creating a semiconductor fin on a substrate; 2) placing three temporary "dummy" gate stacks (first, second, and third) on top of the fin, each with a different width; 3) spacing these dummy gates equally apart; 4) creating source/drain regions (that are the same size and shape) on the exposed parts of the fin; 5) removing the dummy gates, revealing the fin's channel regions; 6) coating the channel regions with a dielectric material; 7) using a mask to cover part of the dielectric layer; 8) removing the exposed dielectric material; 9) removing the mask; and 10) depositing a high-k dielectric and a metal layer to form a first gate stack, a second gate stack, and a third gate stack.
10. A method for fabricating a test structure on a wafer, the method comprising: forming a fin on a substrate; forming a first gate stack over the fin, the first gate stack having a first gate width, the first gate stack including a gate dielectric layer having a first thickness; forming a second gate stack over the fin, the second gate stack having a second gate width, the second gate stack including a gate dielectric layer having a second thickness; and forming a third gate stack over the fin, the third gate stack having a third gate width, the third gate stack including a gate dielectric layer having the second thickness, wherein the first gate stack is arranged a first distance from the second gate stack and the second gate stack is arranged the first distance from the third gate stack, wherein the fin is a same such that the first gate stack, the second gate stack, and the third gate stack are each on the same fin, wherein the first gate stack, the second gate stack, and the third gate stack each have different gate widths on the same fin.
A method for creating a test structure involves: 1) forming a fin on a substrate; 2) creating three gate stacks (first, second, and third) on the *same* fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) placing the gate stacks such that the first is a certain distance from the second, and the second is the same distance from the third.
11. The method of claim 10 , further comprising forming a fourth gate stack over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness.
The method for creating a test structure described above, which involves forming a fin and three gate stacks (first, second, and third) with varying widths and dielectric thicknesses, *also* includes a *fourth* gate stack on the same fin. This fourth gate stack has the *same width* as the *first* gate stack, but it has the *same dielectric thickness* as the *second* gate stack. Thus, it includes: 1) forming a fin on a substrate; 2) creating three gate stacks (first, second, and third) on the same fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) placing the gate stacks such that the first is a certain distance from the second, and the second is the same distance from the third; 4) forming a fourth gate stack over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness.
12. The method of claim 10 , further comprising forming a fifth gate stack over the fin, the fifth gate stack having the second gate width, the fifth gate stack including a gate dielectric layer having the first thickness.
The method for creating a test structure, involving a fin and three gate stacks (first, second, and third) with varying widths and dielectric thicknesses, *also* includes a *fifth* gate stack on the same fin. This fifth gate stack has the *same width* as the *second* gate stack, but it uses the *first* dielectric thickness (the thickness associated with the first gate stack). Thus, it includes: 1) forming a fin on a substrate; 2) creating three gate stacks (first, second, and third) on the same fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) placing the gate stacks such that the first is a certain distance from the second, and the second is the same distance from the third; 4) forming a fifth gate stack over the fin, the fifth gate stack having the second gate width, the fifth gate stack including a gate dielectric layer having the first thickness.
13. The method of claim 10 , further comprising forming a sixth gate stack over the fin, the sixth gate stack having the third gate width, the sixth gate stack including a gate dielectric layer having the first thickness.
The method for creating a test structure, involving a fin and three gate stacks (first, second, and third) with varying widths and dielectric thicknesses, *also* includes a *sixth* gate stack on the same fin. This sixth gate stack has the *same width* as the *third* gate stack, but it uses the *first* dielectric thickness (the thickness associated with the first gate stack). Thus, it includes: 1) forming a fin on a substrate; 2) creating three gate stacks (first, second, and third) on the same fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) placing the gate stacks such that the first is a certain distance from the second, and the second is the same distance from the third; 4) forming a sixth gate stack over the fin, the sixth gate stack having the third gate width, the sixth gate stack including a gate dielectric layer having the first thickness.
14. The method of claim 11 , wherein the fourth gate stack, is arranged the first distance from the third gate stack.
The method for creating a test structure that includes a fin with four gate stacks (first, second, third, and fourth) of varying widths and dielectric thicknesses places the fourth gate stack the same distance from the third gate stack as the other gate stacks are from each other. Thus, it includes: 1) forming a fin on a substrate; 2) creating three gate stacks (first, second, and third) on the same fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) placing the gate stacks such that the first is a certain distance from the second, and the second is the same distance from the third; 4) forming a fourth gate stack over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness, where the fourth gate stack, is arranged the first distance from the third gate stack.
15. A testing structure on a substrate, the structure comprising: a semiconductor fin arranged on the substrate; a first gate stack arranged over the fin, the first gate stack having a first gate width, the first gate stack including a gate dielectric layer having a first thickness; a second gate stack arranged over the fin, the second gate stack having a second gate width, the second gate stack including a gate dielectric layer having a second thickness; and a third gate stack arranged over the fin, the third gate stack having a third gate width, the third gate stack including a gate dielectric layer having the second thickness, wherein the first gate stack is arranged a first distance from the second gate stack and the second gate stack is arranged the first distance from the third gate stack, wherein the fin is a same such that the first gate stack, the second gate stack, and the third gate stack are each on the same fin, wherein the first gate stack, the second gate stack, and the third gate stack each have different gate widths on the same fin.
A test structure comprises: 1) a semiconductor fin on a substrate; 2) three gate stacks (first, second, third) on the *same* fin, each with a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) the gate stacks are arranged such that the first is a certain distance from the second, and the second is the same distance from the third.
16. The structure of claim 15 , further comprising forming a fourth gate stack over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness.
The test structure described above, which involves a fin and three gate stacks (first, second, and third) with varying widths and dielectric thicknesses, *also* includes a *fourth* gate stack on the same fin. This fourth gate stack has the *same width* as the *first* gate stack, but it has the *same dielectric thickness* as the *second* gate stack. Thus, it includes: 1) a semiconductor fin on a substrate; 2) three gate stacks (first, second, third) on the same fin, each with a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) the gate stacks are arranged such that the first is a certain distance from the second, and the second is the same distance from the third; 4) a fourth gate stack arranged over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness.
17. The structure of claim 15 , further comprising forming a fifth gate stack over the fin, the fifth gate stack having the second gate width, the fifth gate stack including a gate dielectric layer having the first thickness.
The test structure, involving a fin and three gate stacks (first, second, and third) with varying widths and dielectric thicknesses, *also* includes a *fifth* gate stack on the same fin. This fifth gate stack has the *same width* as the *second* gate stack, but it uses the *first* dielectric thickness (the thickness associated with the first gate stack). Thus, it includes: 1) a semiconductor fin on a substrate; 2) three gate stacks (first, second, third) on the same fin, each with a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) the gate stacks are arranged such that the first is a certain distance from the second, and the second is the same distance from the third; 4) a fifth gate stack arranged over the fin, the fifth gate stack having the second gate width, the fifth gate stack including a gate dielectric layer having the first thickness.
18. The structure of claim 15 , further comprising forming a sixth gate stack over the fin, the sixth gate stack having the third gate width, the sixth gate stack including a gate dielectric layer having the first thickness.
The test structure, involving a fin and three gate stacks (first, second, and third) with varying widths and dielectric thicknesses, *also* includes a *sixth* gate stack on the same fin. This sixth gate stack has the *same width* as the *third* gate stack, but it uses the *first* dielectric thickness (the thickness associated with the first gate stack). Thus, it includes: 1) a semiconductor fin on a substrate; 2) three gate stacks (first, second, third) on the same fin, each with a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) the gate stacks are arranged such that the first is a certain distance from the second, and the second is the same distance from the third; 4) a sixth gate stack arranged over the fin, the sixth gate stack having the third gate width, the sixth gate stack including a gate dielectric layer having the first thickness.
19. The structure of claim 16 , wherein the fourth gate stack, is arranged the first distance from the third gate stack.
The test structure that includes a fin with four gate stacks (first, second, third, and fourth) of varying widths and dielectric thicknesses places the fourth gate stack the same distance from the third gate stack as the other gate stacks are from each other. Thus, it includes: 1) a semiconductor fin on a substrate; 2) three gate stacks (first, second, and third) on the same fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) the gate stacks are arranged such that the first is a certain distance from the second, and the second is the same distance from the third; 4) a fourth gate stack arranged over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness, where the fourth gate stack, is arranged the first distance from the third gate stack.
20. The structure of claim 17 , wherein the fifth gate stack is arranged the first distance from the fourth gate stack.
The test structure that includes a fin with five gate stacks (first, second, third, fourth, and fifth) of varying widths and dielectric thicknesses places the fifth gate stack the same distance from the fourth gate stack as the other gate stacks are from each other. Thus, it includes: 1) a semiconductor fin on a substrate; 2) three gate stacks (first, second, and third) on the same fin, where each gate stack has a different width; the first gate stack also has a gate dielectric with a first thickness, while the second and third gate stacks use a gate dielectric with a second thickness; and 3) the gate stacks are arranged such that the first is a certain distance from the second, and the second is the same distance from the third; 4) a fourth gate stack arranged over the fin, the fourth gate stack having the first gate width, the first gate stack including a gate dielectric layer having the second thickness; 5) a fifth gate stack arranged over the fin, the fifth gate stack having the second gate width, the fifth gate stack including a gate dielectric layer having the first thickness, where the fifth gate stack is arranged the first distance from the fourth gate stack.
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October 28, 2015
August 8, 2017
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