There is provided a logic device including memory cell units. Each of the memory cell units includes a pair of bit lines arranged corresponding to a column of memory cells, a word line, and an inverter unit connected to the pair of bit lines. The inverter unit includes a first CMOS and a second CMOS. The first CMOS is configured to receive an input signal from one of the pair of bit lines. The first CMOS includes a first MOS transistor and a second MOS transistor. The second CMOS is configured to receive an input signal from the other of the pair of bit lines. The second CMOS includes a third MOS transistor and a fourth MOS transistor. The inverter unit is configured to output a first differential signal and a second differential signal as a data signal.
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1. A reconfigurable logic device configured as a logic element or a connection element, the reconfigurable logic device comprising a plurality of memory cell units, each storing configuration information and configured as the logic element or the connection element, wherein each of the plurality of memory cell units includes a pair of bit lines for logic arranged corresponding to a column of memory cells, a word line for logic, and an inverter unit connected to the pair of bit lines for logic, wherein the inverter unit includes a first CMOS configured to receive an input signal from one of the pair of bit lines for logic, and including a first MOS transistor and a second MOS transistor, and a second CMOS configured to receive an input signal from the other of the pair of bit lines for logic, and including a third MOS transistor and a fourth MOS transistor, and wherein the inverter unit outputs a first differential signal as a set of output signals of the first MOS transistor and the third MOS transistor, and a second differential signal as a set of output signals of the second MOS transistor and the fourth MOS transistor to another memory cell unit as a data signal for logic.
A reconfigurable logic device can function as either a logic element or a connection element. It contains multiple memory cell units that store configuration information determining whether each unit acts as a logic or connection element. Each memory cell unit contains a pair of bit lines, a word line, and an inverter unit. The inverter unit connects to the bit lines. It uses two CMOS circuits: the first CMOS receives an input from one bit line using two MOS transistors, and the second CMOS receives an input from the other bit line using two different MOS transistors. The inverter then outputs two differential signals (derived from the transistor outputs) to another memory cell unit, which act as data signals for logic operations.
2. The reconfigurable logic device according to claim 1 , wherein the memory cell unit is a multi look-up-table.
The reconfigurable logic device as described in Claim 1, which functions as either a logic element or a connection element and contains multiple memory cell units (each with configuration information, bit lines, a word line, and an inverter unit utilizing CMOS circuits and MOS transistors to output differential signals to other memory cell units), where each memory cell unit is a multi look-up-table. This means each cell can store multiple truth tables for complex logic functions, allowing for more flexible and powerful reconfiguration.
3. The reconfigurable logic device according to claim 1 , further comprising an address decoder for logic of a differential four-wire logic configured to receive a data signal for logic outputted from another memory cell unit as an address signal for logic.
The reconfigurable logic device as described in Claim 1, which functions as either a logic element or a connection element and contains multiple memory cell units (each with configuration information, bit lines, a word line, and an inverter unit utilizing CMOS circuits and MOS transistors to output differential signals to other memory cell units), further includes an address decoder for logic that uses differential four-wire logic. This address decoder receives a data signal (for logic) from another memory cell unit and interprets it as an address signal, enabling inter-cell communication and complex routing within the reconfigurable device based on the logic outputs of other cells.
4. The reconfigurable logic device according to claim 1 , comprising an address decoder connected to the plurality of memory cell units, and configured to decode an address signal specifying any memory cell of the plurality of connected memory cell units to output a word line selection signal selecting a word line, wherein each of the plurality of memory cell units includes a pair of bit lines for memory arranged corresponding to a column of memory cells, and a word line for memory connected to the address decoder.
The reconfigurable logic device as described in Claim 1, which functions as either a logic element or a connection element and contains multiple memory cell units (each with configuration information, bit lines, a word line, and an inverter unit utilizing CMOS circuits and MOS transistors to output differential signals to other memory cell units), further includes an address decoder connected to the memory cell units. This decoder decodes an address signal that specifies a particular memory cell, and in response activates a specific word line for memory. Each memory cell unit also has its own pair of bit lines for memory, and a word line for memory that connects to the global address decoder.
5. The reconfigurable logic device according to claim 4 , further comprising a sense amplifier connected to the bit line for memory.
The reconfigurable logic device as described in Claim 4, which contains an address decoder connected to memory cell units, where each unit has memory bit lines and a word line connected to the decoder, further includes a sense amplifier. The sense amplifier is connected to the bit lines used for memory. The sense amplifier amplifies the signals from these bit lines, improving the speed and reliability of reading data stored in the memory cells within the reconfigurable device.
6. A control method for a reconfigurable logic device configured as a logic element or a connection element, and including a plurality of memory cell units; each storing configuration information and configured as the logic element and/or the connection element, wherein each of the plurality of memory cell units includes a pair of bit lines for logic arranged corresponding to a column of memory cells, a word line for logic, and an inverter unit connected to the pair of bit lines for logic, wherein the inverter unit includes a first CMOS including a first MOS transistor and a second MOS transistor, and a second CMOS including a third MOS transistor and a fourth MOS transistor, the control method comprising: receiving, by the inverter unit, an input signal from one of the pair of bit lines for logic; receiving, by the inverter unit, an input signal from the other of the pair of bit lines for logic; and outputting, by the inverter unit, a first differential signal as a set of output signals of the first MOS transistor and the third MOS transistor, and a second differential signal as a set of output signals of the second MOS transistor and the fourth MOS transistor to another memory cell unit as a data signal for logic.
This invention relates to a control method for reconfigurable logic devices, such as field-programmable gate arrays (FPGAs), which can be dynamically configured as either logic elements or connection elements. The device includes multiple memory cell units, each storing configuration information and functioning as a logic or connection element. Each memory cell unit has a pair of bit lines for logic, a word line for logic, and an inverter unit connected to the bit lines. The inverter unit consists of two CMOS circuits: a first CMOS with a first and second MOS transistor, and a second CMOS with a third and fourth MOS transistor. The method involves the inverter unit receiving input signals from both bit lines, processing them, and outputting two differential signals. The first differential signal is generated by the first and third MOS transistors, while the second differential signal is generated by the second and fourth MOS transistors. These differential signals are then transmitted to another memory cell unit as a data signal for logic operations. This approach enhances signal integrity and processing efficiency in reconfigurable logic devices by leveraging differential signaling within the memory cell units.
7. The control method for a reconfigurable logic device according to claim 6 , wherein the memory cell unit is a multi look-up-table.
The method for controlling a reconfigurable logic device as described in Claim 6, which involves inverter units within memory cells receiving input signals from logic bit lines and outputting differential signals, where each memory cell unit is a multi look-up-table. This means the control method operates on a device where cells can store multiple truth tables for complex logic functions, providing greater flexibility in the reconfigurable process.
8. The control method for a reconfigurable logic device according to claim 6 , wherein the reconfigurable logic device further includes an address decoder for logic of a differential four-wire logic, and wherein the address decoder for logic receives a data signal for logic outputted from another memory cell unit as an address signal for logic.
The method for controlling a reconfigurable logic device as described in Claim 6, which involves inverter units within memory cells receiving input signals from logic bit lines and outputting differential signals, further includes a differential four-wire logic address decoder. The decoder receives a data signal for logic from another memory cell unit, and uses this signal as an address. This allows the control method to dynamically route signals within the reconfigurable device based on the logic outputs of other cells.
9. The control method for a reconfigurable logic device according to claim 6 , wherein the reconfigurable logic device includes an address decoder connected to the plurality of memory cell units, wherein each of the plurality of memory cell units includes a pair of bit lines for memory arranged corresponding to a column of memory cells, and a word line for memory connected to the address decoder, and wherein the address decoder receives an address signal specifying any memory cell of the plurality of connected memory cell units, and decodes the address signal to output a word line selection signal selecting a word line.
The method for controlling a reconfigurable logic device as described in Claim 6, which involves inverter units within memory cells receiving input signals from logic bit lines and outputting differential signals, and which includes an address decoder connected to the memory cell units, decodes an address signal and outputs a selection signal. The method involves the address decoder receiving an address that specifies a memory cell. The decoder outputs a signal that selects the word line for that memory cell, controlling access to specific memory locations within the device.
10. The control method for a reconfigurable logic device according to claim 9 , wherein the reconfigurable logic device further includes a sense amplifier connected to the bit line for memory, and wherein the sense amplifier reads data from the bit line for memory.
The method for controlling a reconfigurable logic device as described in Claim 9, which includes an address decoder and bit lines for memory, and decodes address signals to select a word line, further includes a sense amplifier. The sense amplifier is connected to the bit lines for memory, and the control method involves the sense amplifier reading data from these bit lines, allowing the system to retrieve stored configuration or data values.
11. A program for controlling a reconfigurable logic device, wherein the reconfigurable logic device includes a plurality of memory cell units, each storing a program composed of truth table data and configured as a logic element and/or a connection element, wherein each of the plurality of memory cell units includes a pair of bit lines for logic arranged corresponding to a column of memory cells, a word line for logic, and an inverter unit connected to the pair of bit lines for logic, wherein the inverter unit includes a first CMOS including a first MOS transistor and a second MOS transistor, and a second CMOS including a third MOS transistor and a fourth MOS transistor, wherein the inverter unit receives an input signal from one of the pair of bit lines for logic, wherein the inverter unit receives an input signal from the other of the pair of bit lines for logic, and wherein the inverter unit outputs a first differential signal as a set of output signals of the first MOS transistor and the third MOS transistor, and a second differential signal as a set of output signals of the second MOS transistor and the fourth MOS transistor to another memory cell unit as a data signal for logic, the program causing the memory cell unit to execute: processing of outputting a logical operation of a value stored in a memory cell specified by a certain address line to a data line to operate as a logic circuit; and processing of outputting the value stored in the memory cell specified by the certain address line to a data line connected to an address line of another storage unit to operate as a connection circuit.
A program controls a reconfigurable logic device with memory cell units that each store a program as truth table data, configurable as logic/connection elements. Each cell includes logic bit lines, a logic word line, and an inverter with CMOS circuits and MOS transistors. The program causes the memory cell unit to output logical operations of a value stored in a memory cell to a data line, acting as a logic circuit. It also outputs the value from a memory cell to a data line connected to an address line of another storage unit, acting as a connection circuit.
12. The program according to claim 11 , wherein the memory cell unit is a multi look-up-table.
The program for controlling a reconfigurable logic device as described in Claim 11, which utilizes memory cell units configurable as logic or connection elements and truth tables for operation, where each memory cell unit is a multi look-up-table. Thus, the program controls a device where the cells can store and operate on multiple truth tables, enabling more sophisticated and flexible reconfiguration and logic functions.
13. The program according to claim 11 , wherein the reconfigurable logic device further includes an address decoder for logic of a differential four-wire logic, and wherein the address decoder for logic receives a data signal for logic outputted from another memory cell unit as an address signal for logic.
The program for controlling a reconfigurable logic device as described in Claim 11, which utilizes memory cell units configurable as logic or connection elements and truth tables for operation, further utilizes a differential four-wire logic address decoder. The address decoder receives a data signal for logic from another memory cell unit to use as an address signal for logic. This enables the program to control dynamic routing within the reconfigurable device based on logic outputs from other cells.
14. The program according to claim 11 , wherein the reconfigurable logic device includes an address decoder connected to the plurality of memory cell units, wherein each of the plurality of memory cell units includes a pair of bit lines for memory arranged corresponding to a column of memory cells, and a word line for memory connected to the address decoder, and wherein the address decoder receives an address signal specifying any memory cell of the plurality of connected memory cell units, and decodes the address signal to output a word line selection signal selecting a word line.
The program for controlling a reconfigurable logic device as described in Claim 11, which utilizes memory cell units configurable as logic or connection elements and truth tables for operation, where the reconfigurable logic device includes an address decoder connected to the memory cell units. The program involves the address decoder receiving an address signal specifying a memory cell and outputting a word line selection signal. This allows the program to control access to specific memory locations within the device.
15. The program according to claim 14 , wherein the reconfigurable logic device further includes a sense amplifier connected to the bit line for memory, and wherein the sense amplifier reads data from the bit line for memory.
The program for controlling a reconfigurable logic device as described in Claim 14, which includes an address decoder connected to the memory cell units and the program involves the address decoder receiving an address signal specifying a memory cell and outputting a word line selection signal, further utilizes a sense amplifier connected to the bit line for memory. The program involves the sense amplifier reading data from the bit line for memory. This allows the program to retrieve and utilize data stored within the device's memory cells.
16. A storage medium configured to store the program according to claim 11 .
A storage medium is configured to store the program for controlling a reconfigurable logic device, as described in Claim 11. This program utilizes memory cell units configurable as logic or connection elements and truth tables for operation, by processing outputting a logical operation of a value stored in a memory cell specified by a certain address line to a data line to operate as a logic circuit, and processing of outputting the value stored in the memory cell specified by the certain address line to a data line connected to an address line of another storage unit to operate as a connection circuit.
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August 22, 2014
August 8, 2017
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