A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A combined packaged power semiconductor device, comprising: a high-side (HS) MOSFET and a low-side (LS) MOSFET, each of said HS and LS MOSFETs comprising a bottom drain, a top gate and a top source; a lead frame comprising a die paddle and a plurality of pins separated and electrically insulated from said die paddle, wherein said LS MOSFET is flipped and stacked on said die paddle forming an electrical connection between said source of said LS MOSFET and a top surface of said die paddle, as such said source of said LS MOSFET is electrically connected to an exposed bottom surface of said die paddle; a first metal interconnection plate stacked on said drain of said flipped LS MOSFET, wherein said HS MOSFET directly stacked or flipped first and then stacked on said first metal interconnection plate, forming an electrical connection between said drain of said HS MOSFET or said source of said flipped HS MOSFET and said drain of said LS MOSFET through said first metal interconnection plate; a second metal interconnection plate stacked and electrically connected to said source of said HS MOSFET or said drain of said flipped HS MOSFET; an integrated circuit (IC) controller stacked on said die paddle, said IC controller comprising a plurality of electrodes, wherein electrical connections between said plurality of pins, said plurality of electrodes on said IC controller and electrodes of said HS and said flipped LS MOSFETs are formed; and an interposer wherein said gate of flipped LS MOSFET is electrically connected to a conductive top surface of said interposer and a bottom surface of said interposer is stacked on and electrically insulated from said die paddle.
A combined power semiconductor device includes a high-side (HS) MOSFET and a low-side (LS) MOSFET, each with a bottom drain, top gate, and top source. A lead frame contains a die paddle and isolated pins. The LS MOSFET is flipped and attached to the die paddle, grounding its source via the paddle's exposed bottom. A first metal plate connects the HS MOSFET's drain (or source if flipped) to the LS MOSFET's drain. A second metal plate connects to the HS MOSFET's source (or drain if flipped). An IC controller is on the die paddle with electrodes connected to the pins and MOSFETs. An interposer connects the LS MOSFET's gate to its conductive top, with the interposer's bottom insulated from the die paddle. This arrangement reduces size and improves performance through 3D packaging.
2. The combined packaged power semiconductor device of claim 1 , wherein said source of said LS MOSFET is electrically connected to said die paddle through a thick conductive adhesive, wherein said thick conductive adhesive is thick enough such that a top surface of said conductive adhesive between said LS MOSFET and said die paddle and a top surface of a conductive adhesive between said interposer and said LS MOSFET are co-planar.
The combined packaged power semiconductor device, which includes a high-side (HS) MOSFET and a low-side (LS) MOSFET, each with a bottom drain, top gate, and top source; a lead frame containing a die paddle and isolated pins; the LS MOSFET flipped and attached to the die paddle, grounding its source via the paddle's exposed bottom; a first metal plate connecting the HS MOSFET's drain (or source if flipped) to the LS MOSFET's drain; a second metal plate connecting to the HS MOSFET's source (or drain if flipped); an IC controller on the die paddle with electrodes connected to the pins and MOSFETs; and an interposer connecting the LS MOSFET's gate to its conductive top, with the interposer's bottom insulated from the die paddle, uses a thick conductive adhesive to attach the LS MOSFET's source to the die paddle. This adhesive is thick enough to make the top of the adhesive between the LS MOSFET and die paddle co-planar with the top of the adhesive between the interposer and the LS MOSFET.
3. The combined packaged power semiconductor device of claim 1 , wherein a groove is formed at a top surface of said die paddle corresponding to a position of said gate of said LS MOSFET and wherein said interposer is placed in said groove and is electrically insulated from said die paddle.
The combined packaged power semiconductor device, which includes a high-side (HS) MOSFET and a low-side (LS) MOSFET, each with a bottom drain, top gate, and top source; a lead frame containing a die paddle and isolated pins; the LS MOSFET flipped and attached to the die paddle, grounding its source via the paddle's exposed bottom; a first metal plate connecting the HS MOSFET's drain (or source if flipped) to the LS MOSFET's drain; a second metal plate connecting to the HS MOSFET's source (or drain if flipped); an IC controller on the die paddle with electrodes connected to the pins and MOSFETs; and an interposer connecting the LS MOSFET's gate to its conductive top, with the interposer's bottom insulated from the die paddle, includes a groove on the die paddle's top surface, aligned with the LS MOSFET's gate. The interposer sits in this groove and is electrically insulated from the die paddle.
4. The combined packaged power semiconductor device of claim 1 , wherein a groove is formed at a top surface of said die paddle and wherein said interposer is a conductive metal plate with its bottom surface being connected on said die paddle or in said groove through a non-conductive adhesive.
The combined packaged power semiconductor device, which includes a high-side (HS) MOSFET and a low-side (LS) MOSFET, each with a bottom drain, top gate, and top source; a lead frame containing a die paddle and isolated pins; the LS MOSFET flipped and attached to the die paddle, grounding its source via the paddle's exposed bottom; a first metal plate connecting the HS MOSFET's drain (or source if flipped) to the LS MOSFET's drain; a second metal plate connecting to the HS MOSFET's source (or drain if flipped); an IC controller on the die paddle with electrodes connected to the pins and MOSFETs; and an interposer connecting the LS MOSFET's gate to its conductive top, with the interposer's bottom insulated from the die paddle, includes a groove formed on the die paddle. The interposer is a conductive metal plate, and its bottom is attached to the die paddle (either directly or within the groove) using a non-conductive adhesive.
5. The combined packaged power semiconductor device of claim 1 , wherein a groove is formed at a top surface of said die paddle, wherein said interposer comprises a conductive metal upper layer and an insulated lower layer, and wherein a bottom surface of said insulated lower layer is connected on said die paddle or in said groove through an adhesive.
The combined packaged power semiconductor device, which includes a high-side (HS) MOSFET and a low-side (LS) MOSFET, each with a bottom drain, top gate, and top source; a lead frame containing a die paddle and isolated pins; the LS MOSFET flipped and attached to the die paddle, grounding its source via the paddle's exposed bottom; a first metal plate connecting the HS MOSFET's drain (or source if flipped) to the LS MOSFET's drain; a second metal plate connecting to the HS MOSFET's source (or drain if flipped); an IC controller on the die paddle with electrodes connected to the pins and MOSFETs; and an interposer connecting the LS MOSFET's gate to its conductive top, with the interposer's bottom insulated from the die paddle, includes a groove on the die paddle. The interposer has a conductive metal top layer and an insulated bottom layer. The bottom of this insulated layer is attached to the die paddle (or within the groove) using adhesive.
6. The combined packaged power semiconductor device of claim 1 , wherein said IC controller is electrically connected with a top surface of said interposer, forming an electrical connection with said gate of said flipped LS MOSFET.
The combined packaged power semiconductor device, which includes a high-side (HS) MOSFET and a low-side (LS) MOSFET, each with a bottom drain, top gate, and top source; a lead frame containing a die paddle and isolated pins; the LS MOSFET flipped and attached to the die paddle, grounding its source via the paddle's exposed bottom; a first metal plate connecting the HS MOSFET's drain (or source if flipped) to the LS MOSFET's drain; a second metal plate connecting to the HS MOSFET's source (or drain if flipped); an IC controller on the die paddle with electrodes connected to the pins and MOSFETs; and an interposer connecting the LS MOSFET's gate to its conductive top, with the interposer's bottom insulated from the die paddle, includes an IC controller that is electrically connected to the top surface of the interposer, establishing an electrical connection with the gate of the flipped LS MOSFET.
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June 24, 2016
August 15, 2017
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