A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
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1. A semiconductor device comprising: first stack of nanowires arranged on a substrate comprising a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprising a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprising a first semiconductor material and the third nanowire and the fourth nanowire comprising a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
A semiconductor device is built on a substrate. It has two stacked pairs of nanowires. The first pair (nanowire 1 and nanowire 2) are side-by-side, lying flat on the substrate in the same plane. The second pair (nanowire 3 and nanowire 4) are also side-by-side, lying flat on the substrate in the same plane as nanowire 1 and nanowire 2. Nanowire 1 and nanowire 2 are made of a first semiconductor material, while nanowire 3 and nanowire 4 are made of a different, second semiconductor material.
2. The device of claim 1 , wherein the first nanowire and the second nanowire are substantially co-planar in a second plane, the second plane substantially perpendicular to the first plane.
The semiconductor device described previously has the first nanowire and the second nanowire positioned not only side-by-side but also stacked vertically, one on top of the other. This means the two nanowires are in two planes that are perpendicular to each other.
3. The device of claim 1 , wherein the first semiconductor material includes silicon.
In the semiconductor device described previously, the first semiconductor material (used for the first pair of nanowires) is silicon. The second pair of nanowires is made of a different material.
4. The device of claim 1 , wherein the second semiconductor material includes silicon germanium.
In the semiconductor device described previously, the second semiconductor material (used for the second pair of nanowires) is silicon germanium. The first pair of nanowires is made of a different material.
5. The device of claim 1 , further comprising a first gate stack arranged over a channel region of the first stack of nanowires.
The semiconductor device described previously also has a gate stack placed above the channel region of the first pair of nanowires (nanowire 1 and nanowire 2). This gate stack controls the flow of current through that channel region.
6. The device of claim 5 , further comprising spacers arranged adjacent to the first gate stack.
The semiconductor device described previously has a gate stack placed above the first pair of nanowires, and it also has spacers positioned next to that gate stack. These spacers electrically isolate the gate stack from the source and drain regions.
7. The device of claim 6 , further comprising a source/drain region arranged adjacent to the spacers.
The semiconductor device described previously has a gate stack with spacers, and it includes source/drain regions positioned next to the spacers. These source and drain regions provide the electrical contacts for current to flow through the channel controlled by the gate.
8. The device of claim 7 wherein the first nanowire extends through the spacer and into the source/drain region.
In the semiconductor device described previously, the first nanowire of the first pair extends through the spacer and into the source/drain region. This provides a direct connection between the channel and the electrical contact.
9. The device of claim 1 , further comprising a second gate stack arranged over a channel region of the second stack of nanowires.
The semiconductor device described previously includes a second gate stack positioned over the channel region of the second pair of nanowires (nanowire 3 and nanowire 4). This second gate stack controls the current flow through the second pair of nanowires independently of the first pair.
10. The device of claim 9 , further comprising spacers arranged adjacent to the second gate stack.
The semiconductor device described previously has a second gate stack over the second pair of nanowires and also includes spacers placed next to that second gate stack. The spacers electrically isolate this second gate stack.
11. The device of claim 10 , further comprising a source/drain region arranged adjacent to the spacers.
The semiconductor device described previously includes a second gate stack with spacers, and it includes source/drain regions positioned next to the spacers. These source and drain regions provide the electrical contacts for current to flow through the channel controlled by the second gate.
12. A semiconductor device comprising: first stack of nanowires arranged on a substrate comprising a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprising a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, the first nanowire and the second nanowire comprising a first semiconductor material and the third nanowire and the fourth nanowire comprising a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material, and a first gate stack arranged over a channel region of the first nanowire and a channel region of the second nanowire.
A semiconductor device is built on a substrate. It has two stacked pairs of nanowires. The first pair (nanowire 1 and nanowire 2) are side-by-side, lying flat on the substrate in the same plane. The second pair (nanowire 3 and nanowire 4) are also side-by-side, lying flat on the substrate in the same plane as nanowire 1 and nanowire 2. Nanowire 1 and nanowire 2 are made of a first semiconductor material, while nanowire 3 and nanowire 4 are made of a different, second semiconductor material. There is a gate stack placed above the channel regions of both nanowire 1 and nanowire 2 in the first pair.
13. The device of claim 12 , wherein the first nanowire and the second nanowire are substantially co-planar in a second plane, the second plane substantially perpendicular to the first plane.
The semiconductor device described previously with the two nanowire pairs and a gate stack on the first pair, also has the first nanowire and the second nanowire of the first pair positioned not only side-by-side but also stacked vertically, one on top of the other. This means the two nanowires are in two planes that are perpendicular to each other.
14. The device of claim 12 , wherein the first semiconductor material includes silicon.
In the semiconductor device described previously with the two nanowire pairs and a gate stack on the first pair, the first semiconductor material (used for the first pair of nanowires) is silicon. The second pair of nanowires is made of a different material.
15. The device of claim 12 , wherein the second semiconductor material includes silicon germanium.
In the semiconductor device described previously with the two nanowire pairs and a gate stack on the first pair, the second semiconductor material (used for the second pair of nanowires) is silicon germanium. The first pair of nanowires is made of a different material.
16. The device of claim 12 , further comprising spacers arranged adjacent to the first gate stack.
The semiconductor device described previously, with the two nanowire pairs and a gate stack on the first pair, also has spacers positioned next to the gate stack of the first pair. These spacers electrically isolate the gate stack from the source and drain regions.
17. The device of claim 16 , further comprising a source/drain region arranged adjacent to the spacers.
The semiconductor device described previously with the two nanowire pairs, a gate stack and spacers on the first pair, also includes source/drain regions positioned next to the spacers. These source and drain regions provide the electrical contacts for current to flow through the channel controlled by the gate.
18. The device of claim 17 , wherein the first nanowire extends through the spacer and into the source/drain region.
In the semiconductor device described previously with the two nanowire pairs, a gate stack, spacers, and source/drain regions on the first pair, the first nanowire of the first pair extends through the spacer and into the source/drain region. This provides a direct connection between the channel and the electrical contact.
19. The device of claim 12 , further comprising a second gate stack arranged over a channel region of the second stack of nanowires.
The semiconductor device described previously with the two nanowire pairs and a gate stack on the first pair also includes a second gate stack positioned over the channel region of the second pair of nanowires (nanowire 3 and nanowire 4). This second gate stack controls the current flow through the second pair of nanowires independently of the first pair.
20. The device of claim 19 , further comprising spacers arranged adjacent to the second gate stack.
The semiconductor device described previously with the two nanowire pairs, gate stack on the first pair, and a second gate stack over the second pair of nanowires, also includes spacers placed next to that second gate stack. The spacers electrically isolate this second gate stack.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 12, 2016
August 15, 2017
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