Provided is a fully parallel fast Fourier transformer of N-point, where N is a natural number, including a bit-reversal arranging block configured to rearrange an order of N input complex number samples, a plurality of first processors configured to perform, in a plurality of group units, a 16-point FFT on the rearranged complex number samples, a twiddle factor multiplier configured to multiply outputs of the plurality of first processors by twiddle factors, a first group rearranging block configured to rearrange outputs of the twiddle factor multiplier in the plurality of group units, a plurality of second processors configured to perform, in the plurality of group units, 16-point FFT on the complex number samples grouped by the first group rearranging block, and a second group rearranging block configured to rearrange outputs of the plurality of second processors to output under a same arrangement criterion as the first group rearranging block.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A fully parallel fast Fourier transformer of N-point, where N is a natural number, the fully parallel fast Fourier transformer comprising: a bit-reversal arranging block configured to rearrange, according to a bit-reversal permutation, an order of N input complex number samples; a plurality of first processors configured to perform, in a plurality of group units, a 16-point fast Fourier transform (FFT) on the rearranged complex number samples; a twiddle factor multiplier configured to multiply outputs of the plurality of first processors by respective twiddle factors to produce corresponding twiddled outputs of the plurality of first processors; a first group rearranging block configured to rearrange the twiddled outputs of the twiddle factor multiplier in the plurality of group units, so that for each twiddled output corresponding to an i th output of a j th first processor, the twiddled output is grouped into a j th element of an i th group unit of an output of the first group rearranging block; a plurality of second processors configured to perform, in the plurality of group units, 16-point FFT on the complex number samples grouped by the first group rearranging block; and a second group rearranging block configured to rearrange outputs of the plurality of second processors so that for each output of the plurality of second processors, a k th output of an m th second processor corresponds to an m th output of a k th group unit of the output of the second group rearranging block, wherein the m th output of a k th group unit of the second group rearranging block corresponds to an output DOUT[n] of the fully parallel fast Fourier transformer, n=(m−1)+16(k−1).
A fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).
2. The fully parallel fast Fourier transformer of claim 1 , wherein the bit-reversal arranging block allocates an order of the N input complex number samples but rearranges the order in a manner that a bit position of a binary value of the order is switched.
In the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the bit-reversal block reorders the N inputs by reversing the bit order of each input's index. For example, if an input has index 6 (binary 0110), it's moved to index 3 (binary 0011).
3. The fully parallel fast Fourier transformer of claim 1 , wherein the plurality of first processors and the plurality of second processors comprise radix-16 processors configured to perform an FFT operation on the input complex number samples in the plurality of group units.
In the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), both the first-stage and second-stage processors are radix-16 processors. These processors perform the 16-point FFT calculations in the group units.
4. The fully parallel fast Fourier transformer of claim 3 , wherein the plurality of first processors and the plurality of second processors respectively 16 radix-16 processors.
In the fully parallel FFT described in claim 3 (in the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), both the first-stage and second-stage processors are radix-16 processors. These processors perform the 16-point FFT calculations in the group units.), there are specifically 16 radix-16 processors in both the first-stage and the second-stage processor groups.
5. The fully parallel fast Fourier transformer of claim 1 , wherein radix-16 processors included in the plurality of first processors or the plurality of second processors use twiddle factors of W( 1 ), W( 2 ), W( 3 ), W( 4 ), W( 6 ), and W( 9 ) among 16 twiddle factors in complex number multiplication.
In the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the radix-16 processors in the first and/or second stages use a subset of twiddle factors during complex number multiplication. These specific twiddle factors are W(1), W(2), W(3), W(4), W(6), and W(9) out of the 16 possible twiddle factors.
6. The fully parallel fast Fourier transformer of claim 5 , wherein the radix-16 processor comprises 9 complex number multipliers configured to perform complex multiplication operations on the twiddle factors of W( 1 ), W( 2 ), W( 3 ), W( 4 ), W( 6 ), and W( 9 ) and the complex number multiplier for the twiddle factor of W( 4 ) is realized through a sign inversion operation.
In the fully parallel FFT described in claim 5 (in the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the radix-16 processors in the first and/or second stages use a subset of twiddle factors during complex number multiplication. These specific twiddle factors are W(1), W(2), W(3), W(4), W(6), and W(9) out of the 16 possible twiddle factors.), each radix-16 processor contains nine complex number multipliers to handle multiplication by the selected twiddle factors: W(1), W(2), W(3), W(4), W(6), and W(9). The multiplication by the twiddle factor W(4) is implemented using a sign inversion, simplifying the complex multiplication.
7. The fully parallel fast Fourier transformer of claim 5 , wherein for a multiplication operation for each of the twiddle factors of W( 1 ), W( 3 ), and W( 9 ), 3 adders and 3 constant multipliers are used.
In the fully parallel FFT described in claim 5 (in the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the radix-16 processors in the first and/or second stages use a subset of twiddle factors during complex number multiplication. These specific twiddle factors are W(1), W(2), W(3), W(4), W(6), and W(9) out of the 16 possible twiddle factors.), the multiplication by each of the twiddle factors W(1), W(3), and W(9) within a radix-16 processor uses three adders and three constant multipliers.
8. The fully parallel fast Fourier transformer of claim 5 , wherein for a multiplication operation for each of the twiddle factors of W( 2 ) and W( 6 ), 2 adders and 2 constant multipliers are used.
In the fully parallel FFT described in claim 5 (in the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the radix-16 processors in the first and/or second stages use a subset of twiddle factors during complex number multiplication. These specific twiddle factors are W(1), W(2), W(3), W(4), W(6), and W(9) out of the 16 possible twiddle factors.), the multiplication by each of the twiddle factors W(2) and W(6) within a radix-16 processor uses two adders and two constant multipliers.
9. The fully parallel fast Fourier transformer of claim 5 , wherein the radix-16 processor comprises 20 constant multipliers configured to perform complex number multiplication of the twiddle factors.
In the fully parallel FFT described in claim 5 (in the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the radix-16 processors in the first and/or second stages use a subset of twiddle factors during complex number multiplication. These specific twiddle factors are W(1), W(2), W(3), W(4), W(6), and W(9) out of the 16 possible twiddle factors.), each radix-16 processor contains 20 constant multipliers to perform the complex number multiplication with the specific twiddle factors.
10. The fully parallel fast Fourier transformer of claim 9 , wherein the constant multiplier comprises a canonical signed digit (CSD) multiplier realized with shifters and adders.
In the fully parallel FFT described in claim 9 (in the fully parallel FFT described in claim 5 (in the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the radix-16 processors in the first and/or second stages use a subset of twiddle factors during complex number multiplication. These specific twiddle factors are W(1), W(2), W(3), W(4), W(6), and W(9) out of the 16 possible twiddle factors.), each radix-16 processor contains 20 constant multipliers to perform the complex number multiplication with the specific twiddle factors.), the constant multipliers are implemented as canonical signed digit (CSD) multipliers, built from shifters and adders.
11. The fully parallel fast Fourier transformer of claim 1 , wherein at least one of the bit-reversal arranging block, the first group rearranging block, or the second group rearranging block is formed in an interconnection manner without a memory.
In the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), at least one of the bit-reversal block, the first group rearranging block, or the second group rearranging block is implemented as a direct interconnection network without using memory to store intermediate values.
12. The fully parallel fast Fourier transformer of claim 1 , wherein the point number N corresponds to any one length of 32 , 64, 128, 256, 512, 1024, and 2048.
In the fully parallel FFT described in claim 1 (a fully parallel Fast Fourier Transformer (FFT) processes N complex number inputs, where N is a natural number. First, a bit-reversal block reorders the inputs using bit-reversal permutation. Next, multiple first-stage processors, arranged in groups, each perform a 16-point FFT on the reordered data. The outputs of these processors are then multiplied by twiddle factors. A first group rearranging block rearranges the twiddled outputs so that the i-th output of the j-th first processor is grouped into the j-th element of the i-th group in the output of the block. Then, multiple second-stage processors, also in groups, perform a 16-point FFT on the rearranged data. Finally, a second group rearranging block rearranges these outputs such that the k-th output of the m-th second processor becomes the m-th output of the k-th group of the second rearranging block's output. This final output corresponds to the FFT result DOUT[n], where n = (m-1) + 16(k-1).), the value of N, which represents the number of input points for the FFT, can be 32, 64, 128, 256, 512, 1024, or 2048.
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November 10, 2016
August 15, 2017
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