A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for processing instructions in a processor core that includes an architecture with an even execution slice having an even physical register file and an odd execution slice having an odd physical register file, the even and odd execution slices each configured to perform operations specified in a first set of instructions on data from its respective physical register file, and together configured to perform operations specified in a second set of instructions on data stored across both the even and odd physical register files, the method comprising: receiving a first instruction specifying an operation, a target register, and at least one source register, the first instruction being of the first set of instructions; identifying a second instruction upon which content of the at least one source register depends; determining that the second instruction is of the second set of instructions; dispatching, in response to the determining, the first instruction to the even execution slice; performing, using the even execution slice, the operation using content of the at least one source register in the even physical register file to produce a result; writing a first copy of the result to the target register in the even physical register file; writing a second copy of the result to the target register in the odd physical register file; setting an indicator; receiving a third instruction specifying a second set of operations, and a second at least one source register, the second at least one source register being the target register; determining that the third instruction is of the second set of operations; dispatching, in response to the determining that the third instruction is of the second set of operations, the third instruction to the even execution slice and the odd execution slice; detecting that the indicator is set; treating, in response to the detecting, content of the second at least one source register in the odd physical register file as an undefined value for the purposes of the second operation, the content of the second at least one source in the odd physical register file being the second copy of the result; and performing, using the even execution slice and the odd execution slice, the second operation using content of the second at least one source register in the even physical register file and the undefined value to produce a second result.
A processor executes instructions using even and odd execution units, each with its own register file. Some instructions (type 1) operate on data within a single register file, while others (type 2) require data across both. When a type 1 instruction needs data from a register that was last written to by a type 2 instruction, it's handled specially. The type 1 instruction is sent to the even execution unit, which produces a result using the even register file's data. This result is then written to the *same* register in *both* the even and odd register files. An "undefined value" indicator is set for the register in the odd register file. Later, if a type 2 instruction tries to read that register, the odd register file's value is ignored ("undefined"), forcing the instruction to rely on the even register file's value.
2. The method of claim 1 , wherein the second instruction specifies a second operation and a second target register, the second target register being the at least one source register, the method further comprising: receiving the second instruction; performing, using the even execution slice and the odd execution slice, the second operation to produce a second result; writing a copy of a lower portion of the second result to the second target register in the even physical register file, the copy of the lower portion being the content of the at least one source register in the even physical register file; and writing a copy of an upper portion of the second result to the second target register in the odd physical register file.
In the processor described in Claim 1, where a type 1 instruction needs data from a register previously written by a type 2 instruction, the type 2 instruction writes to both register files. Specifically, the type 2 instruction performs an operation and writes the lower half of the result to the even register file and the upper half to the odd register file. This ensures that even when a type 1 instruction uses this data, the even register file contains the correct lower portion, while the odd register file holds the upper portion.
3. The method of claim 2 further comprising: clearing, in association with writing the copy of the upper portion, an indicator, the indicator corresponding with the target register in the odd physical register file.
Expanding on Claim 2, after a type 2 instruction writes to both the even and odd register files and the upper portion is written to the odd register file, an indicator associated with the destination register in the odd register file is cleared. This ensures that subsequent instructions using that register in the odd file will treat its content as valid (rather than "undefined"), unless the primary "undefined value" indicator is also set.
4. The method of claim 1 further comprising: receiving a fourth instruction specifying a second at least one source register, the second at least one source register being the target register; determining that the first instruction and the fourth instruction are both of the first set of instructions; and dispatching, in response to the determining that the first instruction and the fourth instruction are both of the first set of instructions, the fourth instruction to one of the even execution slice and the odd execution slice.
In the processor described in Claim 1, if two type 1 instructions both need to access the same register, one of the even or odd execution units is chosen to execute the second instruction. This means that if a type 1 instruction operates on a register, and then another type 1 instruction needs to operate on the same register, both instructions can be processed without special handling, by routing the second instruction to either the even or odd slice.
5. The method of claim 1 further comprising: setting, in association with writing the first copy of the result, an indicator, the indicator corresponding with the target register in the odd physical register file.
In the processor described in Claim 1, whenever a type 1 instruction's result is written to both the even and odd register files (as a consequence of a previous type 2 instruction dependency), an indicator is set to indicate that the odd register file contains a potentially invalid value for that register. This flag allows the processor to track which registers in the odd file are holding copies of data that might not be fully defined or reliable.
6. The method of claim 1 , wherein the indicator is at least one bit which corresponds with the target register in the odd physical register file.
In the processor described in Claim 1, the "undefined value" indicator is implemented using a single bit for each register in the odd physical register file. This bit flags whether the register's content should be treated as "undefined" when accessed by certain instructions.
7. A method for processing instructions in a processor core that includes an architecture with an even execution slice having an even physical register file and an odd execution slice having an odd physical register file, the even and odd execution slices each configured to perform operations specified in a first set of instructions on data from its respective physical register file, and together configured to perform operations specified in a second set of instructions on data stored across both the even and odd physical register files, the method comprising: receiving an instruction specifying an operation and at least one source register, the instruction being of the second set of instructions; detecting that an indicator is set; treating, in response to the detecting, content of the at least one source register in the odd physical register file as an undefined value for the purposes of the operation; and performing, using the even execution slice and the odd execution slice, the operation using content of the at least one source register in the even physical register file and the undefined value to produce a result.
A processor executes instructions using even and odd execution units, each with its own register file. Some instructions (type 1) operate on data within a single register file, while others (type 2) require data across both. If a type 2 instruction tries to read a register and an "undefined value" indicator is set for that register in the odd register file, the odd register file's value is ignored. The type 2 instruction then executes using the valid data from the even register file and the "undefined" value.
8. The method of claim 7 further comprising: receiving a second instruction specifying a second operation and a target register, the second instruction being of the first set of instructions, and the target register being the at least one source register; performing the second operation using one of the even execution slice and the odd execution slice to produce a second result; writing a first copy of the second result to the target register in the even physical register file, the first copy being the content of the at least one source register in the even physical register file; writing a second copy of the second result to the target register in the odd physical register file, the second copy being the content of the at least one source register in the odd physical register file; and setting the indicator.
Building on Claim 7, if a type 2 instruction has previously flagged a register as "undefined," and then a type 1 instruction needs to write to that same register, the type 1 instruction writes a copy of its result to *both* the even and odd register files. The "undefined value" indicator is then set, ensuring that any future type 2 instruction accessing that register knows to disregard the potentially invalid data in the odd register file.
9. The method of claim 7 , wherein the indicator is at least one bit which corresponds with the at least one source register in the odd physical register file.
In the processor described in Claim 7, the "undefined value" indicator is implemented using a single bit for each register in the odd physical register file. This bit flags whether the register's content should be treated as "undefined" when accessed by type 2 instructions.
10. The method of claim 7 , wherein the instruction further specifies a second source register, wherein the indicator corresponds with the at least one source register in the odd physical register file, and wherein the performing the operation further uses content of the second source register in the even physical register file and content of the second source register in the odd physical register file to produce the result, the method further comprising: detecting that a second indicator is clear, the second indicator corresponding with the second source register in the odd physical register file; and treating, in response to the detecting that the second indicator is clear, content of the second source register in the odd physical register file as itself for the purposes of the operation.
Expanding on Claim 7, if a type 2 instruction uses two source registers, the primary register has the undefined value indicator set to treat its value from the odd register file as "undefined". A second indicator determines if the second source register has valid data. If the second source register's indicator is clear, the type 2 instruction uses the value from the second source register in the odd register file as if it were a valid value.
11. The method of claim 7 , wherein the architecture further includes a second even execution slice having a second even physical register file and a second odd execution slice having a second odd physical register file, wherein the second even execution slice is configured to perform operations specified in the first set of instructions on data from the second even physical register file, wherein the second even and second odd execution slices are together configured to perform operations specified in the second set of instructions on data stored across both the second even and second odd physical register files, and wherein the even, second even, odd, and second odd execution slices are together configured to perform operations specified in a third set of instructions on data stored across all of the even, second even, odd, and second odd physical register files.
Building on Claim 7, the processor's architecture is extended to include a second pair of even and odd execution units, each with its own register file. The first pair of execution units handles type 1 and type 2 instructions as described before. The second pair also handles type 1 and 2 instructions on its own register files. A third set of instructions (type 3) can access data from *all four* register files (both even and odd from both execution unit pairs).
12. The method of claim 7 , wherein the instruction further specifies a target register, the method further comprising: writing a copy of a lower portion of the result to the target register in the even physical register file; and writing a copy of an upper portion of the result to the target register in the odd physical register file.
Expanding on Claim 7, after the execution of a type 2 instruction that ignores the odd register's "undefined" value, the resulting data is split into two portions. The lower portion of the result is written to the target register in the even register file, and the upper portion is written to the target register in the odd register file.
13. The method of claim 12 , wherein the indicator corresponds with the at least one source register in the odd physical register file, the method further comprising: clearing, in association with writing the copy of the upper portion, a second indicator, the second indicator corresponding with the target register in the odd physical register file.
Building on Claim 12, after a type 2 instruction writes its result, where the "undefined value" indicator corresponds to one source register, and the result is split and written to the target register, a *second* "undefined value" indicator (specific to the *target* register in the *odd* register file) is cleared. This clears the undefined value flag associated with the output/target register in the odd physical register file.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 18, 2014
August 22, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.