An inductor array chip includes a magnetic laminated body and a plurality of inductors. The magnetic laminated body includes a plurality of stacked magnetic layers. The plurality of inductors are arranged inside the magnetic laminated body. The inductance of a first inductor differs from the inductance of a second inductor. The inductors include a plurality of coil-shaped conductors and via-hole conductors. The plurality of coil-shaped conductors are arranged between the magnetic layers. The via-hole conductors electrically connect the plurality of coil-shaped conductors. The inductors include a plurality of inductors in which the section sizes of the coil-shaped conductors differ from one another.
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1. An inductor array chip comprising: a magnetic laminated body including a plurality of stacked magnetic layers; and a plurality of inductors arranged inside the magnetic laminated body, inductances of the plurality of inductors being different from one another; wherein each of the plurality of inductors includes: a plurality of coil-shaped conductors arranged between the magnetic layers; and a via-hole conductor that electrically connects the plurality of coil-shaped conductors; the plurality of coil-shaped conductors of one of the plurality of inductors have a different section size from a section size of the plurality of coil-shaped conductors of another one of the plurality of inductors; each of the one of the plurality of inductors and the another one of the plurality of inductors includes a same number of the coil-shaped conductors; at least one of the plurality of inductors includes a plurality of inductor units connected in parallel to one another; and each of the plurality of inductor units overlap each other in plan view.
An inductor array chip has a layered magnetic body and multiple inductors inside. Each inductor has a different inductance value. These inductors are made of coil-shaped conductors between the magnetic layers, connected by via-holes. At least two of the inductors have coil-shaped conductors with different cross-sectional sizes but the same number of coils. Furthermore, at least one of the inductors includes multiple inductor units connected in parallel that overlap when viewed from above.
2. The inductor array chip according to claim 1 , wherein an inductance of one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively small section size is greater than an inductance of another one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively large section size.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, is further configured such that an inductor with smaller coil cross-sections has a *higher* inductance than one with larger coil cross-sections.
3. The inductor array chip according to claim 1 , wherein an inductance of one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively small section size is smaller than an inductance of another one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively large section size.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, is further configured such that an inductor with smaller coil cross-sections has a *lower* inductance than one with larger coil cross-sections.
4. The inductor array chip according to claim 1 , wherein in the one of the plurality of inductors and the another of the plurality of inductors in which the plurality of coil-shaped conductors have different section sizes, coil diameters of the coil-shaped conductors differ from one another.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, includes inductors where the coil diameters differ as well. The inductors with different cross sectional areas also have different coil diameters from each other.
5. The inductor array chip according to claim 4 , wherein one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively small section size has a coil diameter smaller than a coil diameter of another one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively large section size.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, including inductors where the coil diameters differ as well, is configured so that an inductor with smaller coil cross-sections also has a *smaller* coil diameter than an inductor with larger coil cross-sections.
6. The inductor array chip according to claim 4 , wherein one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively small section size has a coil diameter greater than a coil diameter of another one of the plurality of inductors including a plurality of coil-shaped conductors having a relatively large section size.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, including inductors where the coil diameters differ as well, is configured so that an inductor with smaller coil cross-sections also has a *larger* coil diameter than an inductor with larger coil cross-sections.
7. The inductor array chip according to claim 1 , wherein the plurality of inductors include a plurality of inductors each including a plurality of inductor units; and in the plurality of inductors each including a plurality of inductor units, connection configurations of the plurality of inductor units differ from one another.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, has multiple inductors each consisting of multiple inductor units. The way these inductor units are connected together (e.g., series, parallel) is different between at least two of these multi-unit inductors.
8. The inductor array chip according to claim 1 , wherein a first of the plurality of inductors includes one inductor unit and a second of the plurality of inductors includes a plurality of inductor units.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, and differing coil cross-sectional sizes, has at least one inductor built from a *single* inductor unit, while another inductor is constructed from *multiple* inductor units.
9. The inductor array chip according to claim 8 , wherein the plurality of inductor units of the second of the plurality of inductors are connected to each other in parallel.
An inductor array chip, as described previously with a layered magnetic body containing inductors of differing inductance, coil-shaped conductors connected by vias, differing coil cross-sectional sizes, including one inductor with a single inductor unit and another with multiple inductor units, is designed such that the multiple inductor units are connected in parallel.
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April 14, 2015
August 29, 2017
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