An integrated circuit is provided for self-repair of a memory array. The circuit includes first word lines coupled to first memory rows of the memory array, one first word line for each bit of a line address word, second word lines coupled to one or more spare memory rows of the memory array. Repair configuration data is stored in memory cells within the integrated circuit to direct memory accesses to spare memory rows rather than dysfunctional first memory rows. A memory cell may be based on a correlated electron switch (CES). A built-in self-test circuit is provided to facilitate setting of repair configuration data. The repair data may be reconfigurable, enabling operating margins to be improved by testing under various operating conditions.
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1. An apparatus for self-repair of a memory array, the apparatus comprising: a plurality of first word lines coupled to a plurality of first memory rows of the memory array, one first word line for each bit of a line address word; one or more second word lines coupled to one or more of second memory rows of the memory array; and an address decoder circuit responsive to an address word and configured to generate therefrom a signal on a selected word line of the first and second word lines; for each first word line of the plurality of first word lines: a first storage element configured to store a repair value; and a first logic circuit configured to prevent or enable selection of the first word line dependent upon the stored repair value; for each second word line of the one or more second word lines: a plurality of second storage elements operable to store a line address of a first memory row to be repaired; a third storage element configured to store a repair-enable value when a first memory row coupled to the second word line is to be used to repair a first memory row of the plurality of first memory rows, and a second logic circuit responsive to the address word and configured to generate a signal on the second word line if the stored line address matches the address word and the stored repair-enable value indicates that the second memory row coupled to the second word line is to be used to repair the first memory row.
A self-repairing memory system includes a memory array with regular rows and spare rows. Each regular row has a word line, and each spare row has a word line. When an address is sent to the memory, an address decoder selects one of these word lines. Each regular word line has a storage element that holds a "repair value". A logic circuit uses this repair value to determine whether to enable or prevent the selection of that word line. Each spare word line has storage elements that hold the address of a faulty regular row it's meant to replace, and a "repair-enable" value. A logic circuit activates a spare row's word line only if the incoming address matches the stored faulty row's address and the "repair-enable" value indicates that this spare row should be used for repair.
2. The apparatus of claim 1 , where the first, second and third storage elements, the first and second logic circuits, and the address decoder are formed in a single integrated circuit.
The self-repairing memory system of claim 1, where the storage elements, logic circuits, and address decoder for the self-repairing memory array are all integrated onto a single chip. This consolidation enhances efficiency and reduces overall system size.
3. The apparatus of claim 2 , further comprising the memory array, where the memory array is formed in the single integrated circuit.
The self-repairing memory system of claim 2, further includes the memory array itself being integrated on the same single chip as the storage elements, logic circuits, and address decoder. This full integration allows for a compact and efficient self-repairing memory solution.
4. The apparatus of claim 3 , where the memory array comprises an array of correlated electron switch (CES) memory cells.
The self-repairing memory system of claim 3, where the memory array, integrated on the single chip, utilizes correlated electron switch (CES) memory cells. This type of memory cell offers unique characteristics for the self-repairing capabilities of the system.
5. The apparatus of claim 1 , where at least one of the first, second and third storage elements comprises a non-volatile memory.
In the self-repairing memory system described in claim 1, at least one of the storage elements that store repair values or addresses uses non-volatile memory. This ensures that repair configurations persist even when power is removed from the system.
6. The apparatus of claim 1 , where at least one of the first, second and third storage elements comprises a correlated electron switch (CES).
In the self-repairing memory system described in claim 1, at least one of the storage elements uses correlated electron switch (CES) memory. CES offers distinct advantages for storing configuration data within the self-repairing architecture.
7. A non-transient computer readable medium containing instructions of a hardware description language defining the apparatus of claim 1 .
A computer-readable storage medium holds a hardware description language (HDL) representation of the self-repairing memory system as described in claim 1. This HDL code can be used to manufacture the described memory system with built-in self-repair capabilities.
8. An apparatus for self-repair of a memory array, the apparatus comprising: a plurality of first word lines coupled to a plurality of first memory rows of the memory array, one first word line for each bit of a line address word; one or more second word lines coupled to one or more of second memory rows of the memory array; an address decoder circuit responsive to an address word and configured to generate therefrom a signal on a selected word line of the first and second word lines; for each first word line of the plurality of first word lines: a first storage element configured to store a repair value; and a first logic circuit configured to enable selection of the first word line when the stored repair value is set to a logical-1 value and further configured to prevent selection of the first word line when the stored repair value is reset to a logical-0 value; compare logic configured to assert a reset signal when a value read from a row of the memory array couple to the first word line does not match an expected value; and write logic configured to reset the repair value stored in the first storage element to a logical-0 value when the reset signal is asserted.
A self-repairing memory system features regular and spare memory rows, each with a corresponding word line. An address decoder selects a word line based on an input address. Each regular word line has a storage element holding a "repair value" and logic that enables the word line only when the repair value is logical-1, preventing selection when it's logical-0. Compare logic monitors data read from memory rows. If the read data doesn't match the expected data, a reset signal is triggered. Write logic then resets the repair value in the corresponding storage element to logical-0, effectively disabling the faulty row.
9. The apparatus of claim 8 , where the first storage elements, the first logic circuit, the address decoder, the compare logic and the write logic are formed in a single integrated circuit.
The self-repairing memory system as described in claim 8, where the storage elements, the word line logic circuit, address decoder, data comparison logic, and write logic for the self-repairing memory array are all integrated onto a single chip.
10. The apparatus of claim 9 , further comprising the memory array, where the memory array is formed in the single integrated circuit.
The self-repairing memory system as described in claim 9, further includes the memory array being integrated on the same single chip as the storage elements, logic circuits, address decoder, data comparison logic, and write logic.
11. The apparatus of claim 10 , where the memory array comprises an array of correlated electron switch (CES) memory cells.
The self-repairing memory system described in claim 10, where the memory array, integrated on a single chip, consists of correlated electron switch (CES) memory cells.
12. The apparatus of claim 8 , where the first logic circuit comprises read logic configured to read a repair value stored in the first storage element.
In the self-repairing memory system of claim 8, the logic circuit that controls the first word line's selection includes read logic to read the repair value stored in the first storage element.
13. The apparatus of claim 8 , where at least one of the first storage elements comprises a non-volatile memory.
In the self-repairing memory system as described in claim 8, at least one of the storage elements storing repair values utilizes non-volatile memory, ensuring the values are retained even without power.
14. The apparatus of claim 8 , where at least one of the first storage elements comprises a correlated electron switch (CES).
In the self-repairing memory system of claim 8, at least one of the storage elements storing repair values uses a correlated electron switch (CES) memory cell.
15. The apparatus of claim 8 , where the write logic is further configured to set the repair value to a logical-1 in response to a global set signal.
In the self-repairing memory system of claim 8, the write logic can also set the repair value to a logical-1 upon receiving a global set signal, allowing for re-enabling previously disabled rows.
16. A non-transient computer readable medium containing instructions of a hardware description language defining the apparatus of claim 8 .
A computer-readable medium stores instructions written in a hardware description language (HDL) that defines the self-repairing memory system described in claim 8.
17. A method for configuring a memory array to provide improved operating margin, the method comprising: testing the memory array under a plurality of operating conditions to identify defective rows of the memory array and determine associated repair configuration data; determining a most stringent operating condition for which sufficient spare rows are available to replace the defective rows; and configuring the memory array using the repair configuration data associated with the most stringent operating condition for which sufficient spare rows are available to replace the defective rows, whereby the operating margin of the memory array is improved when the memory array is operated under less stringent operating conditions.
A method for improving the operating margin of a memory array through self-repair involves testing the array under various operating conditions to find defective rows and determine corresponding repair data. The method identifies the most demanding condition where enough spare rows exist to replace the defective ones. The memory array is then configured using the repair data from this stringent condition. This optimizes the memory to function robustly even under less demanding, normal operating conditions.
18. The method of claim 17 , where testing the memory array under the plurality of operating conditions to identify defective rows of the memory and determine associated repair configuration data comprises: testing the memory array under a first operating condition to identify defective rows of the memory array and associated repair configuration data; and for one or more iterations: testing the memory array under a more stringent operating condition if sufficient spare rows are available to replace the defective rows; and testing the memory array under a less stringent operating condition if sufficient spare rows are not available to replace the defective rows.
The method of claim 17, where testing the memory array involves an iterative process. First, the array is tested under an initial condition. Subsequent iterations involve testing under progressively stricter conditions if sufficient spare rows are available for defective rows. Conversely, if spare rows are insufficient, testing occurs under less strict conditions to establish optimal repair configuration data.
19. The method of claim 17 , where testing the memory array comprises: for each row of the memory array: testing the row by comparing values read back from the memory array with expected values; and replacing the row with a spare row of the memory array and updating repair configuration data stored in memory cells when the row is defective and a spare row of the memory array is available.
The memory array testing process in claim 17 involves testing each row by comparing read-back values against expected values. If a row is found to be defective and a spare row is available, the defective row is replaced with the spare, and the repair configuration data is updated accordingly.
20. The method of claim 19 , where testing the row and replacing the row with a spare row of the memory array when the row is defective and a spare row of the memory array is available is performed by an integrated self-repair circuit.
The memory array testing and replacement method of claim 19 is performed by an integrated self-repair circuit, automating the detection and correction of defective rows.
21. The method of claim 17 , where configuring the memory array using repair configuration data associated the most stringent operating condition for which sufficient spare rows are available to replace the defective rows comprises storing the repair configuration data in memory cells.
Configuring the memory array in claim 17 involves storing the generated repair configuration data in memory cells within the array itself, providing on-chip storage of the repair settings.
22. The method of claim 21 , where storing a bit of the repair configuration data in memory cells comprises causing a state transition in a correlated electron switch (CES).
Storing repair configuration data within memory cells, as mentioned in claim 21, involves causing a state transition within a correlated electron switch (CES) to represent each bit of the repair data.
23. An apparatus for self-repair of a memory array, the apparatus comprising: a plurality of first word lines coupled to a plurality of first memory rows of the memory array, one first word line for each bit of a line address word; one or more second word lines coupled to one or more of second memory rows of the memory array; a storage element comprising one or more correlated electron switches; and a logic circuit operable to select between a first word line of the plurality of first word lines and a second word line of the one or more second word lines dependent upon one or more values stored in the storage element, where the second word line is selected if the one or more stored values indicate that the first word line couples to a first memory row that is to be repaired.
A self-repairing memory array includes regular memory rows with corresponding word lines and spare memory rows with their own word lines. A storage element, made of one or more correlated electron switches (CES), holds values indicating which regular rows need repair. A logic circuit selects either a regular row's word line or a spare row's word line based on these stored values. The spare row is selected if the stored values indicate that the corresponding regular row is defective and needs to be replaced.
24. The apparatus of claim 23 , further comprising the memory array, where the memory array, storage element and logic circuit are formed in a single integrated circuit.
The self-repairing memory array in claim 23, which includes the memory array itself, the storage element containing the repair data, and the selection logic, are all manufactured on a single integrated circuit.
25. The apparatus of claim 23 , further comprising an integrated self-repair circuit, where the integrated self-repair circuit, storage element and logic circuit are formed in a single integrated circuit.
The self-repairing memory system in claim 23 contains an integrated self-repair circuit that along with the storage element and selection logic are manufactured on a single integrated circuit.
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December 16, 2016
September 19, 2017
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