The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.
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1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate having a surface; forming at least one fin over the surface of the semiconductor substrate; forming a mask layer on side surfaces of the fin; forming insulation layer trenches in the semiconductor substrate by etching the semiconductor substrate using the mask layer as an etching mask; forming silicon oxide layers on side surfaces of the insulation layer trenches under the fins and a lower portion of the fin; forming first nitrogen-doped oxide layers by doping nitrogen into the silicon oxide layers; and filling the insulation layer trenches with nitrogen-doped silicon oxide to form second nitrogen-doped silicon oxide layers, the first nitrogen-doped silicon oxide layers and the second nitrogen-doped silicon oxide layer form an insulation layer under the fin.
A method for making a semiconductor device involves creating a fin structure on a semiconductor substrate. A mask is applied to the fin's sides. Insulation trenches are then etched into the substrate using the mask. Silicon oxide layers are grown inside these trenches, beneath the fins. These oxide layers are then doped with nitrogen to form a first nitrogen-doped oxide. The trenches are filled with nitrogen-doped silicon oxide, creating a second nitrogen-doped oxide layer. The combination of the first and second nitrogen-doped oxide layers forms an insulation layer under the fin.
2. The method according to claim 1 , wherein: the silicon oxide layers are formed by an oxidation process.
The method for fabricating a semiconductor device as previously described involves growing the silicon oxide layers using an oxidation process inside insulation trenches etched into the semiconductor substrate beneath a fin structure. A mask protects the fin during trench formation. These oxide layers are later doped with nitrogen to form an insulation layer. The silicon oxide layers are formed via oxidation process to improve layer quality and uniformity.
3. The method according to claim 2 , wherein: a reaction gas of the oxidation process is oxygen; a temperature of the oxidation process is in a range of approximately 100° C.-1000° C.; a flow rate of the reaction gas is in a range of approximately 20 sccm-2000 sccm; a pressure of the oxidation process is in a range of approximately 0.01 Torr-50 Torr; and a power of the oxidation process is in a range of approximately 50 W-10000 W.
In the semiconductor fabrication method involving oxidation to create silicon oxide layers within insulation trenches under a fin structure, the oxidation process uses oxygen gas as a reaction gas. The oxidation temperature ranges from 100°C to 1000°C. The oxygen flow rate is between 20 sccm and 2000 sccm. The oxidation pressure is maintained between 0.01 Torr and 50 Torr. The oxidation process uses power between 50 W and 10000 W. These parameters are used to control the growth of silicon oxide layers.
4. The method according to claim 1 , wherein forming the insulation layer trenches comprises: forming first trenches in the semiconductor substrate by etching the semiconductor substrate using the mask layer as an etching mask; and extending side surfaces of the first trenches under the fin.
When creating the insulation trenches in the semiconductor fabrication method, the process involves two steps. First, initial trenches are etched into the semiconductor substrate using a mask layer on the fins as an etching mask. Second, the side surfaces of these initial trenches are extended laterally under the fin structure. This extension creates a larger area for insulation material to improve the heat dissipation and short channel effect.
5. The method according to claim 4 , wherein: the first trenches are formed by a dry etching process; and the side surfaces of the first trenches are extended by a wet etching process.
In the method for creating insulation trenches under a fin structure, the initial trenches are formed using a dry etching process. The side surfaces of these trenches are then extended using a wet etching process. The combination of dry and wet etching enables precise control over trench dimensions and under-fin extension.
6. The method according to claim 5 , wherein: an etching gas of the dry etching process includes one of CF 4 and NF 3 ; a flow rate of the etching gas is in a range of approximately 10 sccm-2000 sccm; a pressure of the dry etching process is in a range of approximately 0.01 mTorr-50 mTorr; and a power of the dry etching process is in a range of approximately 50 W-10000 W.
The dry etching step to create initial trenches in the semiconductor fabrication process uses either CF4 or NF3 as an etching gas. The gas flow rate is between 10 sccm and 2000 sccm. The pressure during dry etching is between 0.01 mTorr and 50 mTorr. The power applied during dry etching is between 50 W and 10000 W. These parameters optimize the etching rate and profile.
7. The method according to claim 5 , wherein: an etching solution of the wet etching process is a diluted HF solution; and a volume ratio of HF and water in the diluted HF solution is in a range of approximately 1:300-1:1000.
During the wet etching step to extend the side surfaces of trenches under the fin, a diluted HF (hydrofluoric acid) solution is used. The volume ratio of HF to water in the diluted solution is between 1:300 and 1:1000. The dilute HF solution allows for controlled and isotropic etching of the silicon substrate under the fin.
8. The method according to claim 1 , wherein forming the first nitrogen-doped layers comprises: generating a nitrogen plasma to treat the silicon oxide layers, and doping nitrogen into the silicon oxide layers.
The step of forming the first nitrogen-doped oxide layers involves generating a nitrogen plasma and using this plasma to treat the silicon oxide layers. This nitrogen plasma treatment dopes nitrogen atoms into the silicon oxide layers, enhancing their insulating properties.
9. The method according to claim 8 , wherein generating the nitrogen plasma comprises: introducing one of N 2 , NH 3 and N 2 H 2 into a plasma generator.
When generating the nitrogen plasma, either N2, NH3, or N2H2 gas is introduced into a plasma generator. This ensures a sufficient supply of nitrogen radicals or ions for the doping process of forming nitrogen-doped oxide layers.
10. The method according to claim 9 , wherein: a flow rate of one of N 2 , NH 3 and N 2 H 2 is in a range of approximately 20 sccm-2000 sccm; a pressure in the plasma generator is in a range of approximately 0.01 Torr-50 Torr; and a power of the plasma generator is in a range of approximately 50 W-10000 W.
When using N2, NH3, or N2H2 gas to generate the nitrogen plasma, the flow rate of the gas is between 20 sccm and 2000 sccm. The pressure inside the plasma generator is between 0.01 Torr and 50 Torr. The power applied to the plasma generator is between 50 W and 10000 W. These parameters control the plasma density and nitrogen incorporation rate.
11. The method according to claim 1 , before filling the nitrogen-doped silicon oxide into the insulation layer trenches, further comprising: removing the mask layer.
Before filling the insulation trenches with nitrogen-doped silicon oxide, the mask layer on the fin is removed. This ensures the nitrogen-doped silicon oxide fills the trenches completely.
12. The method according to claim 11 , wherein: the mask layer is made of silicon nitride; and the mask layer is removed by a wet etching process using phosphoric acid as an etching solution.
The mask layer, made of silicon nitride, is removed using a wet etching process with phosphoric acid as the etching solution. Phosphoric acid selectively etches silicon nitride without significantly affecting other materials, ensuring clean removal of the mask layer.
13. The method according to claim 11 , wherein: a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.
The thickness of the insulation layer, which is formed by nitrogen-doped silicon oxide, is between 2 Angstroms and 200 Angstroms. This thickness range is carefully selected to optimize the insulation properties and reduce short channel effects.
14. A method for fabricating a fin field-effect transistor according to claim 1 , further comprising: forming a gate structure crossing over the fin, and covering top and side surfaces of the fin over the semiconductor substrate; and forming a source in the fin at one side of the gate structure and a drain in the fin at another side of the gate structure.
The method further includes fabricating a fin field-effect transistor. A gate structure is formed crossing over the fin, covering its top and side surfaces. A source region is created in the fin on one side of the gate, and a drain region is created in the fin on the other side of the gate. This completes the fabrication of a FinFET with improved insulation.
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June 1, 2016
October 24, 2017
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