A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.
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1. A circuit comprising: a first memory cell having a first port and a second port; a data control circuit configured to provide first data to be written from the first port to the first memory cell and to provide second data based on information of the first data, wherein, the second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
A memory circuit has a memory cell with two ports (first and second). A data control circuit provides first data to be written to the memory cell via the first port. It also generates second data based on the first data. If the second port causes a "write disturb" (unintended change) to the first port, then the second port writes the second data to the memory cell. The write disturb detection relies on the state of the first memory cell's write enable signal (whether writing is currently allowed).
2. The circuit of claim 1 , wherein the data control circuit comprises a data driver associated with the second port; and a data circuit configured to provide the information of the first data for the data driver to generate the second data.
This memory circuit, as described above, includes a data driver associated with the second port. A data circuit provides information about the first data to the data driver. The data driver uses this information to generate the second data written through the second port of the memory cell. The second port writes the second data based on information of the first data, wherein, the second port writes to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
3. The circuit of claim 1 , comprising a second memory cell; and a detection circuit configured to detect the write disturb based on a row address of the first port and a row address of a port of the second memory cell.
This memory circuit, as described above, also has a second memory cell. A detection circuit detects the "write disturb" (unintended change to the first port) based on the row address of the first port of the first memory cell and the row address of a port of the second memory cell. The second port writes the second data based on information of the first data, wherein, the second port writes to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
4. The circuit of claim 1 , comprising a second memory cell; and a logic circuit configured to generate a detection signal indicating a write disturb condition based on whether the first port and a port of the second memory cell are of a same row, and the write enable signal of the first memory cell.
This memory circuit, as described above, also has a second memory cell. A logic circuit generates a signal indicating a "write disturb" condition. This is based on whether the first port of the first memory cell and a port of the second memory cell are on the same row and the state of the write enable signal of the first memory cell. The second port writes the second data based on information of the first data, wherein, the second port writes to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
5. The circuit of claim 4 , wherein the logic circuit is configured to generate the detection signal based on a write enable signal of the second memory cell.
In the memory circuit described where a logic circuit generates a signal indicating a write disturb condition based on whether the first port of the first memory cell and a port of the second memory cell are on the same row and the state of the write enable signal of the first memory cell, the logic circuit also uses the write enable signal of the second memory cell to generate this write disturb detection signal.
6. The circuit of claim 1 , wherein the first port includes a first control line; the second port includes a second control line; and the second data corresponds to an activation time period of the first control line and an activation time period of the second control line.
In the memory circuit described above, the first port has a first control line, and the second port has a second control line. The second data that's written to the memory cell through the second port corresponds to how long the first control line is active AND how long the second control line is active. The second port writes the second data based on information of the first data, wherein, the second port writes to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
7. The circuit of claim 1 , wherein the first port includes a first control line; the second port includes a second control line; and the write disturb is caused by an activation time period of the first control line and an activation time period of the second control line.
In the memory circuit described above, the first port has a first control line, and the second port has a second control line. The "write disturb" (unintended change to first port data) is caused by how long the first control line is active AND how long the second control line is active. The second port writes the second data based on information of the first data, wherein, the second port writes to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
8. The circuit of claim 1 , wherein the first port includes a first control line; the second port includes a second control line; the circuit comprises a second memory cell having a first port and a second port; the first port of the second memory cell includes the first control line; and the second port of the second memory cell includes the second control line.
In the memory circuit described above, the first port has a first control line, and the second port has a second control line. The circuit also has a second memory cell that also has a first and second port. The first port of the *second* memory cell uses the *same* first control line as the first port of the *first* memory cell. The second port of the *second* memory cell uses the *same* second control line as the second port of the *first* memory cell. The second port writes the second data based on information of the first data, wherein, the second port writes to the first memory cell based on a detection of a write disturb caused by the second port to the first port, wherein the write disturb detection is based on a state of a write enable signal of the first memory cell.
9. A method comprising: performing a first write operation to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
A memory writing method involves: 1) Writing first data to a memory cell through its first port. This port is associated with a first control line. 2) Writing second data to the *same* memory cell through its second port. The second port has a second control line. The second data is based on information of the first data. This second write happens only if a "write disturb" is detected, determined by looking at the write enable signal. The second write operation's timing is based on how long the first and second control lines are active.
10. The method of claim 9 , wherein a write disturb occurs to the first write operation based on a read condition of the second port.
In the memory writing method described above, a "write disturb" (unintended change to data) to the first write operation is triggered when the second port is being read from. The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
11. The method of claim 9 , wherein the first control line and the second control line are active during a same time period.
In the memory writing method described above, where first data is written to the first port with a first control line and second data is written to the second port with a second control line based on disturb detection, the first and second control lines are active at the *same* time. The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
12. The method of claim 9 , comprising accessing the first memory cell based on the first port of the first memory cell; and accessing a second memory cell based on a port of the second memory cell, the port of the second memory cell including the second control line.
In the memory writing method described above, where first data is written to the first port with a first control line and second data is written to the second port with a second control line based on disturb detection, the method also accesses a *second* memory cell through *its* port. This port of the second memory cell also uses the second control line. The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
13. The method of claim 9 , comprising determining whether the first port of the first memory cell and a port of a second memory cell are of a same row.
In the memory writing method described above, where first data is written to the first port with a first control line and second data is written to the second port with a second control line based on disturb detection, the method includes a step to check if the first port of the first memory cell and a port of a second memory cell are on the *same* row in the memory array. The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
14. The method of claim 9 , wherein the first control line is associated with a first port of a second memory cell; the second control line is associated with a second port of the second memory cell; and the first memory cell and the second memory cell are on a same row of a memory array.
In the memory writing method described above, where first data is written to the first port with a first control line and second data is written to the second port with a second control line based on disturb detection, the first control line is also used by the first port of a *second* memory cell. The second control line is also used by the second port of the second memory cell. Furthermore, the first and second memory cells are on the *same* row of the memory array. The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
15. The method of claim 14 wherein the second port of the second memory cell is write accessed; and the method comprises causing the first port of the second memory cell to perform a write operation based on information of data to be write accessed to the second memory cell.
Consider the memory writing method where a first memory cell has a first port with a first control line, and a second port with a second control line. A second memory cell also has a first and second port that use the same first and second control lines. The first and second memory cells are on the same row. Now, if you *write* to the second port of the *second* memory cell, the *first* port of the *second* memory cell performs a write operation *also*. The data written to the first port of the second memory cell is based on information of the data that was written to the second port. The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
16. The method of claim 9 , wherein a data driver associated with the second port generates the second data based on information of the first data.
In the memory writing method described above, where first data is written to the first port with a first control line and second data is written to the second port with a second control line based on disturb detection, a data driver associated with the *second* port of the *first* memory cell generates the *second* data. This data driver uses information from the *first* data (that was written to the first port). The first write operation is to a first memory cell based on a first port of the first memory cell, the first port corresponding to a first control line and first data; and performing a second write operation to the first memory cell based on a second port of the first memory cell, the second port corresponding to a second control line and second data generated based on information of the first data, wherein the second write operation is performed based on a write disturb detection based on a state of a write enable signal, wherein performing the second write operation is based on a time period corresponding to an activation period of the first control line and an activation period of the second control line.
17. A method comprising: write accessing a first memory cell based on first data and a first port of the first memory cell; write or read accessing a second memory cell based on a port of the second memory cell; determining whether the first port of the first memory cell and the port of the second memory cell are of a same row; and based on a result of the determining and on a write disturb detection based on a state of a write enable signal, generating second data for a second port of the first memory cell based on information of the first data; and causing the second port of the first memory cell to write the second data to the first memory cell.
A memory write method: Write data to the first port of the first memory cell. Either write or read to a port of a second memory cell. Check if the first port of the first memory cell and the port of the second memory cell are on the same row. If they are, AND a write disturb is detected, generate a second data for the *second* port of the *first* memory cell based on information from the first data. Then, write the second data, via the second port, to the first memory cell. The write disturb detection based on a state of a write enable signal.
18. The method of claim 17 , wherein the port of the second memory cell is one of a first port associated with a first control line or a second port associated with a second control line; and the method comprises causing the first port of the second memory cell to perform a write operation based on information of third data of a write access to the second memory cell.
Consider the memory write method that writes data to the first port of the first memory cell, accesses the second memory cell, determines if the first port of the first memory cell and the port of the second memory cell are on the same row, and if so and a write disturb is detected, generates a second data for the second port of the first memory cell based on information of the first data and causes the second port to write the second data to the first memory cell. The port of the *second* memory cell is either its first port (associated with a first control line) or its second port (associated with a second control line). Furthermore, if a write access occurs on the second memory cell, the method forces the first port of the *second* memory cell to also perform a write operation, with its data based on the data that was written to the second memory cell. The write disturb detection based on a state of a write enable signal.
19. The method of claim 18 , wherein the second data for the second port of the first memory cell corresponds to a time period that the first control line and the second control line are both active.
In the memory write method involving writing to a first memory cell's first port, accessing a second memory cell, checking for row overlap, detecting write disturb based on the write enable signal and writing second data to first memory cell's second port based on first data, wherein a write access occurs on the second memory cell, the method forces the first port of the *second* memory cell to also perform a write operation, with its data based on the data that was written to the second memory cell, the second data written to the *second* port of the *first* memory cell is based on the duration when the first control line *AND* the second control line are both active.
20. The method of claim 17 , wherein a data driver associated with the second port of the first memory cell generates the second data based on the information of the first data.
In the memory write method involving writing to a first memory cell's first port, accessing a second memory cell, checking for row overlap, detecting write disturb based on the write enable signal and writing second data to first memory cell's second port based on first data, the second data is generated by a data driver associated with the *second* port of the *first* memory cell. This data driver creates the second data using information from the *first* data.
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November 19, 2014
October 31, 2017
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