A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The semiconductor layer comprises: a first portion extending in the first direction and facing a plurality of the control gate electrodes; and a second portion provided on a closer side to the substrate than this first portion. A film thickness of the first portion in the second direction is larger than a film thickness of the second portion in the second direction. A crystal grain included in the first portion is larger than a crystal grain included in the second portion.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor memory device, comprising: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a first semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the first semiconductor layer, the first semiconductor layer comprising: a first portion extending in the first direction and facing the control gate electrode; and a second portion provided on a closer side to the substrate than the first portion, a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, and a crystal grain included in the first portion being larger than a crystal grain included in the second portion.
A semiconductor memory device has control gate electrodes arranged in a row on top of a substrate. A semiconductor layer runs parallel to the row of electrodes and is separated from them by a gate insulating layer. The semiconductor layer has two sections: a top section facing the electrodes and a bottom section closer to the substrate. The top section is thicker than the bottom section, and the crystal grains in the top section are larger than the crystal grains in the bottom section. This design aims to improve memory performance by optimizing the crystal structure of the semiconductor layer.
2. The semiconductor memory device according to claim 1 , wherein the first portion includes a crystal grain larger than a film thickness of the first portion in the second direction.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with a top and bottom section, and a gate insulating layer (as described in Claim 1), the crystal grain size in the top section of the semiconductor layer is larger than the thickness of that top section. This configuration relates crystal grain size to layer thickness to influence electron mobility or charge storage characteristics within the memory cell.
3. The semiconductor memory device according to claim 1 , wherein the crystal grain included in the first portion is larger than a film thickness of the first portion in the second portion, and the crystal grain included in the second portion is smaller than a film thickness of the second portion in the second portion.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with a top and bottom section, and a gate insulating layer (as described in Claim 1), the crystal grains in the top section are larger than the thickness of the top section, while the crystal grains in the bottom section are smaller than the thickness of the bottom section. This specific grain size to thickness ratio across the two sections is intended to optimize charge transport and retention properties within the device, enhancing its performance as a memory cell.
4. The semiconductor memory device according to claim 1 , further comprising a second semiconductor layer connected to an end of the first semiconductor layer on a side of the substrate.
The semiconductor memory device with control gate electrodes, a semiconductor layer with a top and bottom section, and a gate insulating layer (as described in Claim 1) also includes a second semiconductor layer connected to the bottom of the first semiconductor layer, near the substrate. The inclusion of the second layer potentially functions as a contact layer or a buffer layer to facilitate electrical connections or improve overall device stability.
5. The semiconductor memory device according to claim 1 , wherein the first semiconductor layer further comprises a third portion provided between the first portion and the second portion, and the third portion includes a metal atom.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with a top and bottom section, and a gate insulating layer (as described in Claim 1), the semiconductor layer has a third section between the top and bottom sections. This third section contains metal atoms. The metal atoms may be included to adjust the electrical characteristics of the semiconductor layer, such as its conductivity or work function, or to facilitate silicide formation for improved contact.
6. The semiconductor memory device according to claim 5 , wherein the third portion includes a silicide.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top, middle (containing metal atoms), and bottom sections, and a gate insulating layer (as described in Claim 5), the third section contains a silicide. Using a silicide in this middle section can create a low-resistance contact between the top and bottom sections of the semiconductor layer, improving charge transport and overall device performance.
7. The semiconductor memory device according to claim 1 , wherein the gate insulating layer includes a charge accumulation part.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with a top and bottom section, and a gate insulating layer (as described in Claim 1), the gate insulating layer has a part that stores electrical charge. This charge accumulation part enables the memory device to store information by trapping charge within the insulating layer, similar to how flash memory operates.
8. A semiconductor memory device, comprising: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a first semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the first semiconductor layer, the first semiconductor layer comprising: a first portion extending in the first direction and facing the control gate electrode; and a second portion provided on a closer side to the substrate than the first portion, a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, the first portion including a crystal grain larger than the film thickness of the first portion in the second direction, and the second portion including a monocrystal.
A semiconductor memory device includes control gate electrodes arranged in a row on a substrate. A semiconductor layer runs parallel to the electrodes and is separated by a gate insulating layer. The semiconductor layer has two sections: a top section facing the electrodes and a bottom section closer to the substrate. The top section is thicker than the bottom section. The crystal grain size in the top section is larger than its thickness, and the bottom section is made of a single crystal (monocrystal). This combines a large-grained, thick top section with a single-crystal bottom section for optimized charge transport or storage.
9. The semiconductor memory device according to claim 8 , further comprising a second semiconductor layer connected to an end of the first semiconductor layer on a side of the substrate.
The semiconductor memory device with control gate electrodes, a semiconductor layer with a top and bottom section where the top section grains are larger than its thickness and the bottom section is a monocrystal, and a gate insulating layer (as described in Claim 8) also includes a second semiconductor layer connected to the bottom of the first semiconductor layer. This second layer is intended to provide better electrical contact or serve as a buffer layer for the device.
10. The semiconductor memory device according to claim 9 , wherein the second semiconductor layer includes a monocrystal, and the monocrystal included in the second portion of the first semiconductor layer has an orientation plane aligned with that of the monocrystal included in the second semiconductor layer.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top and bottom sections, the top section grains larger than its thickness, the bottom section being a monocrystal, a second semiconductor layer connected to the first, and a gate insulating layer (as described in Claim 9), both the second semiconductor layer and the bottom section of the first semiconductor layer are monocrystals, and their crystal orientations are aligned. This alignment improves charge transport between the two layers.
11. The semiconductor memory device according to claim 8 , wherein the first semiconductor layer further comprises a third portion provided between the first portion and the second portion, and the third portion includes a metal atom.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top (grains larger than thickness) and bottom (monocrystal) sections, and a gate insulating layer (as described in Claim 8), the first semiconductor layer also includes a third section between the top and bottom sections, which contains metal atoms. The metal atoms are added to modify the electrical properties of the semiconductor, potentially creating a more efficient interface or charge trap.
12. The semiconductor memory device according to claim 11 , wherein the third portion includes a silicide.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top, middle (containing metal atoms), and bottom sections, and a gate insulating layer (as described in Claim 11), the third section contains a silicide. The silicide provides a low-resistance contact between the top and bottom sections.
13. The semiconductor memory device according to claim 8 , wherein the gate insulating layer includes a charge accumulation part.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top (grains larger than thickness) and bottom (monocrystal) sections, and a gate insulating layer (as described in Claim 8), the gate insulating layer includes a part that stores electrical charge. This allows the device to function as a memory element by trapping charges in the insulating layer.
14. A semiconductor memory device, comprising: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer, the semiconductor layer comprising: a first portion extending in the first direction and facing the control gate electrode; a second portion provided on a closer side to the substrate than the first portion; and a third portion provided between the first portion and the second portion, a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, and the third portion including a metal atom of nickel (Ni), cobalt (Co), aluminum (Al), or palladium (Pd).
A semiconductor memory device has control gate electrodes arranged in a row on a substrate. A semiconductor layer runs parallel to the electrodes and is separated by a gate insulating layer. The semiconductor layer has three sections: a top section facing the electrodes, a bottom section closer to the substrate, and a middle section between the top and bottom sections. The top section is thicker than the bottom section, and the middle section contains metal atoms, specifically nickel, cobalt, aluminum, or palladium. These metals are added to modify the semiconductor's electrical characteristics or promote silicide formation.
15. The semiconductor memory device according to claim 14 , wherein the third portion includes a silicide.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top, middle (containing nickel, cobalt, aluminum or palladium), and bottom sections, and a gate insulating layer (as described in Claim 14), the middle section contains a silicide. Forming a silicide in the middle section with these metals improves conductivity and device performance.
16. The semiconductor memory device according to claim 14 , wherein the gate insulating layer includes a charge accumulation part.
In the semiconductor memory device with control gate electrodes, a semiconductor layer with top, middle (containing nickel, cobalt, aluminum, or palladium), and bottom sections, and a gate insulating layer (as described in Claim 14), the gate insulating layer includes a part that stores electrical charge. This enables charge trapping and memory functionality.
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September 21, 2016
October 31, 2017
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