A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.
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1. An interconnect structure, comprising: a substrate having an opening therein; a dielectric block present in the opening of the substrate, the dielectric block having at least one first via therein, wherein the dielectric block has a dielectric constant smaller than that of the substrate; a first conductor present in the first via of the dielectric block, the first conductor having a first portion protruding out of the first via, wherein a top surface of the first portion of the first conductor is in contact with a bottom surface of the dielectric block; a pad present on the first conductor; a dielectric layer present on the substrate and having at least one second via therein to expose the pad; and a second conductor present in the second via and electrically connected to the first conductor through the pad.
An interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
2. The interconnect structure of claim 1 , wherein the first conductor is present on a sidewall of the first via.
In the interconnect structure, the conductor within the dielectric block's via is not a solid filling, but rather a layer present on the sidewall of the via. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
3. The interconnect structure of claim 1 , further comprising: a plug present in the first via.
The interconnect structure has a plug inside the first via. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
4. The interconnect structure of claim 1 , further comprising: a shielding element present between the dielectric block and a sidewall of the opening.
In the interconnect structure, a shielding element is placed between the dielectric block and the sidewall of the opening in the substrate. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
5. The interconnect structure of claim 1 , further comprising: at least one conductive line present on the substrate and electrically connected to the first conductor.
This interconnect structure also includes at least one conductive line on the substrate, electrically connected to the first conductor within the dielectric block's via. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
6. The interconnect structure of claim 1 , wherein there is at least two of the first via in the dielectric block, the interconnect structure further comprising: at least two conductive lines present on the substrate and respectively electrically connected to at least two of the first conductors in the two of the first vias.
The interconnect structure contains at least two vias within the dielectric block. Two conductive lines are present on the substrate, each individually connected to one of the conductors in the two vias. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
7. The interconnect structure of claim 1 , wherein the dielectric block is substantially level with a top surface of the substrate.
The top surface of the dielectric block is essentially level with the top surface of the substrate. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
8. The interconnect structure of claim 1 , wherein the opening is a through hole.
The opening in the substrate is a through-hole, meaning it extends completely through the substrate. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
9. The interconnect structure of claim 1 , wherein the first conductor has a second portion protruding out of the first via, and the pad is present on the second portion of the first conductor.
The first conductor protrudes above the via in two portions. The pad is situated on the second protruding portion of the first conductor. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
10. The interconnect structure of claim 9 , further comprising: a plug present in the first via, wherein the pad is further present on the plug.
The interconnect structure is designed for semiconductor devices, addressing challenges in electrical connectivity between different layers of a chip. The structure includes a first via formed in a dielectric layer, a pad positioned on the dielectric layer and aligned with the first via, and a conductive plug within the first via. The pad is also present on the plug, enhancing electrical contact and reducing resistance. The plug ensures reliable signal transmission through the via, while the pad provides a stable connection point for subsequent wiring or bonding. This configuration improves signal integrity and manufacturing yield by minimizing defects in the interconnect path. The structure is particularly useful in advanced semiconductor fabrication where precise alignment and low-resistance connections are critical. The plug and pad combination ensures robust electrical performance, even in high-density interconnect designs. The dielectric layer isolates the interconnect from adjacent structures, preventing signal interference. This invention is relevant to semiconductor manufacturing, integrated circuit design, and microelectronics packaging, where efficient and reliable interconnects are essential for device functionality.
11. The interconnect structure of claim 10 , wherein the plug is substantially level with a top surface of the second portion of the first conductor.
The plug in the first via is substantially level with the top surface of the second protruding portion of the first conductor. This interconnect structure includes a plug present in the first via, where the pad sits on top of the plug as well as on top of the protruding second portion of the first conductor. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad. The first conductor has a second portion protruding out of the first via, and the pad is present on the second portion of the first conductor.
12. The interconnect structure of claim 10 , wherein a width of the pad is substantially equal to a width of the second portion of the first conductor.
The width of the pad is about the same as the width of the second protruding portion of the first conductor. This interconnect structure includes a plug present in the first via, where the pad sits on top of the plug as well as on top of the protruding second portion of the first conductor. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad. The first conductor has a second portion protruding out of the first via, and the pad is present on the second portion of the first conductor.
13. The interconnect structure of claim 1 , wherein the second via is substantially tapered toward the pad.
The upper via in the dielectric layer is tapered, becoming narrower as it approaches the pad. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
14. The interconnect structure of claim 1 , wherein the second via is filled with the second conductor.
The upper via is completely filled with the second conductor material. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
15. The interconnect structure of claim 1 , further comprising: at least one conductive line present on a surface of the dielectric layer and electrically connected to the second conductor.
The interconnect also includes at least one conductive line on the surface of the dielectric layer, and this line is electrically connected to the second conductor that fills the upper via. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
16. The interconnect structure of claim 4 , wherein the dielectric block and the first conductor therein are surrounded by the shielding element.
The shielding element completely surrounds the dielectric block and the conductor within it. In the interconnect structure, a shielding element is placed between the dielectric block and the sidewall of the opening in the substrate. The interconnect structure comprises a substrate with an opening. A dielectric block resides within this opening, possessing at least one via (a vertical connection). This dielectric block has a lower dielectric constant than the substrate material. A conductor occupies the via, extending slightly above it. The top of this conductor makes direct contact with the bottom surface of the dielectric block. A pad sits on top of this conductor. A dielectric layer covers the substrate, featuring another via that exposes the pad. A second conductor fills this upper via and connects electrically to the first conductor via the pad.
17. An interconnect structure, comprising: a substrate having an opening therein; a low-k dielectric block present in the opening of the substrate, the low-k dielectric block having at least one first via therein; a first conductor present in the first via of the dielectric block, wherein a top surface of a first portion of the first conductor is in contact with a bottom surface of the dielectric block; a pad over the first conductor; a dielectric layer present on the substrate and having at least one second via therein; and a second conductor present in the second via, the second conductor being over and in contact with the pad.
An interconnect structure comprises a substrate with an opening, and a low-k dielectric block resides within this opening. The dielectric block has at least one via. A conductor is present in the via, with its top surface in contact with the bottom surface of the dielectric block. A pad is placed above the conductor. A dielectric layer is present on the substrate with at least one second via. A second conductor is present within the second via and makes contact with the pad.
18. The interconnect structure of claim 17 , wherein the low-k dielectric block has a dielectric constant smaller than that of the substrate.
The low-k dielectric block has a dielectric constant smaller than the substrate. An interconnect structure comprises a substrate with an opening, and a low-k dielectric block resides within this opening. The dielectric block has at least one via. A conductor is present in the via, with its top surface in contact with the bottom surface of the dielectric block. A pad is placed above the conductor. A dielectric layer is present on the substrate with at least one second via. A second conductor is present within the second via and makes contact with the pad.
19. An interconnect structure, comprising: a substrate having an opening therein; a dielectric block present in the opening of the substrate, the dielectric block having a plurality of vias therein, wherein the dielectric block has a dielectric constant smaller than that of the substrate; a plurality of conductors respectively present in the vias of the dielectric block and separated from each other by the dielectric block, wherein at least one of the conductors has a portion protruding out of at least one of the vias, and a top surface of the portion of the at least one of the conductors is in contact with a bottom surface of the dielectric block; a pad present on the at least one of the conductors; a dielectric layer present on the substrate and having at least one second via therein to expose the pad; and a second conductor present in the second via and electrically connected to the at least one of the conductors through the pad.
An interconnect structure comprises a substrate with an opening. A dielectric block with multiple vias is placed within the opening; this block has a lower dielectric constant than the substrate. Conductors are present within each via, separated from each other by the dielectric block. At least one conductor has a portion protruding from its via, making top-surface contact with the bottom of the dielectric block. A pad is present on top of this conductor. A dielectric layer on the substrate contains at least one second via that exposes the pad. Finally, a second conductor is located within the second via and electrically connected to the aforementioned conductor through the pad.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 4, 2016
October 31, 2017
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