Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.
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1. A method of manufacturing a fin field effect transistor (FinFET) semiconductor device, the method comprising: forming a first fin and a second fin on a substrate, the first fin comprising a same material as the material of the substrate; masking the first fin while a substance is introduced to alter a material of the second fin, the altered material of the second fin being a layer of different material than the material of the substrate; after the forming the first fin and the second fin, forming an isolation region between the first fin and the second fin; forming a SiO 2 layer over the first fin, the second fin, and a top surface of the isolation region using a plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; after forming the SiO 2 layer, post-treating the SiO 2 layer with an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and after post-treating the SiO 2 layer, performing an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device.
A method for manufacturing a FinFET semiconductor device involves these steps: First, create a first fin and a second fin on a substrate, where the first fin is made of the same material as the substrate. Next, mask the first fin and introduce a substance to change the material of the second fin, making it a different material than the substrate. Then, form an isolation region between the first and second fins. Deposit a silicon dioxide (SiO2) layer over both fins and the isolation region's top surface using plasma-enhanced atomic layer deposition (PE-ALD) at a power between 10 and 500 Watts and a temperature between 200 and 400 degrees Celsius. After depositing the SiO2 layer, treat it with an in-situ oxygen plasma at a temperature of 600 degrees Celsius or less. Finally, anneal the SiO2 layer, which forms the gate dielectric of the FinFET device.
2. The method according to claim 1 , wherein providing the substrate comprises the first fin comprising a same material as the material of the substrate.
This method for manufacturing a FinFET semiconductor device builds upon the process of forming a first fin and a second fin on a substrate, masking the first fin while a substance is introduced to alter the material of the second fin, the altered material of the second fin being a layer of different material than the material of the substrate; after the forming the first fin and the second fin, forming an isolation region between the first fin and the second fin; forming a SiO 2 layer over the first fin, the second fin, and a top surface of the isolation region using a plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; after forming the SiO 2 layer, post-treating the SiO 2 layer with an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and after post-treating the SiO 2 layer, performing an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device. It specifies that the substrate includes a first fin which comprises the same material as the material of the substrate.
3. The method according to claim 2 , wherein the material of the substrate comprises Si or Ge, or wherein the layer of different material comprises SiGe, SiC, or Sn.
Expanding on the FinFET manufacturing method of forming a first fin and a second fin on a substrate, masking the first fin while a substance is introduced to alter the material of the second fin, the altered material of the second fin being a layer of different material than the material of the substrate; after the forming the first fin and the second fin, forming an isolation region between the first fin and the second fin; forming a SiO 2 layer over the first fin, the second fin, and a top surface of the isolation region using a plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; after forming the SiO 2 layer, post-treating the SiO 2 layer with an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and after post-treating the SiO 2 layer, performing an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device; where the substrate includes a first fin which comprises the same material as the material of the substrate. In this variation, the substrate material is either Silicon (Si) or Germanium (Ge). The different material used for the second fin can be Silicon Germanium (SiGe), Silicon Carbide (SiC), or Tin (Sn).
4. The method according to claim 1 , wherein forming the SiO 2 layer comprises forming a substantially conformal layer having a conformality of about 95% or greater.
This FinFET manufacturing process, involving forming a first fin and a second fin on a substrate, masking the first fin while a substance is introduced to alter the material of the second fin, the altered material of the second fin being a layer of different material than the material of the substrate; after the forming the first fin and the second fin, forming an isolation region between the first fin and the second fin; forming a SiO 2 layer over the first fin, the second fin, and a top surface of the isolation region using a plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; after forming the SiO 2 layer, post-treating the SiO 2 layer with an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and after post-treating the SiO 2 layer, performing an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device, requires the SiO2 layer to be substantially conformal, achieving a conformality of 95% or greater. Conformal deposition ensures uniform coverage over complex 3D structures.
5. The method according to claim 1 , wherein the in-situ O 2 plasma treatment comprises a power of about 200 Watts to about 500 Watts.
This method, where we form a first fin and a second fin on a substrate, masking the first fin while a substance is introduced to alter the material of the second fin, the altered material of the second fin being a layer of different material than the material of the substrate; after the forming the first fin and the second fin, forming an isolation region between the first fin and the second fin; forming a SiO 2 layer over the first fin, the second fin, and a top surface of the isolation region using a plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; after forming the SiO 2 layer, post-treating the SiO 2 layer with an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and after post-treating the SiO 2 layer, performing an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device, uses an in-situ oxygen plasma treatment with a power between 200 and 500 Watts.
6. The method according to claim 1 , wherein the anneal process comprises at least one of an ultraviolet (UV) light exposure processor a high pressure oxidation process.
Continuing with the FinFET manufacturing method of forming a first fin and a second fin on a substrate, masking the first fin while a substance is introduced to alter the material of the second fin, the altered material of the second fin being a layer of different material than the material of the substrate; after the forming the first fin and the second fin, forming an isolation region between the first fin and the second fin; forming a SiO 2 layer over the first fin, the second fin, and a top surface of the isolation region using a plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; after forming the SiO 2 layer, post-treating the SiO 2 layer with an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and after post-treating the SiO 2 layer, performing an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device, the anneal process involves either ultraviolet (UV) light exposure or a high-pressure oxidation process.
7. A method of manufacturing a semiconductor device, the method comprising: forming a fin field effect transistor (FinFET) device comprising: forming a plurality of first fins over a substrate, the plurality of first fins comprising a same material as a material of the substrate; forming a plurality of second fins over the substrate, the plurality of second fins comprising a different material than the material of the substrate; forming a plurality of shallow trench isolation (STI) regions between the plurality of first fins and the plurality of second fins, wherein top surfaces of the plurality of STI regions are recessed below top surfaces of the plurality of first fins and the plurality of second fins, the plurality of STI regions comprising a first material layer; forming an oxide over the plurality of first fins, the plurality of second fins, and the top surfaces of the plurality of STI regions using an atomic layer deposition (ALD) process, wherein material of the oxide comprises a second material layer that is different than the first material layer; after forming the oxide, performing a first post-treatment process, the first post-treatment process comprising an ultraviolet (UV) light treatment process in ambient O 3 , wherein the UV light treatment process is performed at a temperature of from about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, or for a time period of from about 1 minute to about 10 minutes; and after the first post-treatment process, performing a second post-treatment process, the second post-treatment process comprising an oxygen-containing post-treatment process, the second post-treatment process different than the first post-treatment process.
A method for manufacturing a semiconductor device involves creating a FinFET structure. First, form multiple first fins and multiple second fins on a substrate. The first fins are made of the same material as the substrate, while the second fins are made of a different material. Then, create shallow trench isolation (STI) regions between the two sets of fins, where the tops of the STI regions are lower than the tops of the fins. The STI regions are composed of a first material. Next, deposit an oxide layer over the fins and the STI regions using atomic layer deposition (ALD). This oxide layer is made of a second material, different from the STI material. A first post-treatment process is then performed, consisting of UV light treatment in an ozone atmosphere at a temperature between 300 and 450 degrees Celsius, a pressure between 4 and 20 Torr, and for a duration between 1 and 10 minutes. Finally, perform a second post-treatment process involving an oxygen-containing environment, and it must be different than the first post-treatment process.
8. The method according to claim 7 , wherein forming the oxide comprises using a plasma-enhanced ALD (PE-ALD) process.
This semiconductor manufacturing method for creating FinFETs, involving forming a plurality of first fins over a substrate, the plurality of first fins comprising a same material as a material of the substrate; forming a plurality of second fins over the substrate, the plurality of second fins comprising a different material than the material of the substrate; forming a plurality of shallow trench isolation (STI) regions between the plurality of first fins and the plurality of second fins, wherein top surfaces of the plurality of STI regions are recessed below top surfaces of the plurality of first fins and the plurality of second fins, the plurality of STI regions comprising a first material layer; forming an oxide over the plurality of first fins, the plurality of second fins, and the top surfaces of the plurality of STI regions using an atomic layer deposition (ALD) process, wherein material of the oxide comprises a second material layer that is different than the first material layer; after forming the oxide, performing a first post-treatment process, the first post-treatment process comprising an ultraviolet (UV) light treatment process in ambient O 3 , wherein the UV light treatment process is performed at a temperature of from about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, or for a time period of from about 1 minute to about 10 minutes; and after the first post-treatment process, performing a second post-treatment process, the second post-treatment process comprising an oxygen-containing post-treatment process, the second post-treatment process different than the first post-treatment process, specifies that the oxide layer is formed using plasma-enhanced ALD (PE-ALD).
9. The method according to claim 7 , wherein performing the second post-treatment process comprises an anneal process in ambient O 2 .
The process of manufacturing FinFETs, involving forming a plurality of first fins over a substrate, the plurality of first fins comprising a same material as a material of the substrate; forming a plurality of second fins over the substrate, the plurality of second fins comprising a different material than the material of the substrate; forming a plurality of shallow trench isolation (STI) regions between the plurality of first fins and the plurality of second fins, wherein top surfaces of the plurality of STI regions are recessed below top surfaces of the plurality of first fins and the plurality of second fins, the plurality of STI regions comprising a first material layer; forming an oxide over the plurality of first fins, the plurality of second fins, and the top surfaces of the plurality of STI regions using an atomic layer deposition (ALD) process, wherein material of the oxide comprises a second material layer that is different than the first material layer; after forming the oxide, performing a first post-treatment process, the first post-treatment process comprising an ultraviolet (UV) light treatment process in ambient O 3 , wherein the UV light treatment process is performed at a temperature of from about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, or for a time period of from about 1 minute to about 10 minutes; and after the first post-treatment process, performing a second post-treatment process, the second post-treatment process comprising an oxygen-containing post-treatment process, the second post-treatment process different than the first post-treatment process, defines the second post-treatment process as an anneal performed in an oxygen environment.
10. The method according to claim 9 , wherein the anneal process comprises a temperature of about 400 degrees C. to about 600 degrees C. or a pressure of about 5 atmospheres (ATM) to about 20 ATM.
In this FinFET manufacturing process of forming a plurality of first fins over a substrate, the plurality of first fins comprising a same material as a material of the substrate; forming a plurality of second fins over the substrate, the plurality of second fins comprising a different material than the material of the substrate; forming a plurality of shallow trench isolation (STI) regions between the plurality of first fins and the plurality of second fins, wherein top surfaces of the plurality of STI regions are recessed below top surfaces of the plurality of first fins and the plurality of second fins, the plurality of STI regions comprising a first material layer; forming an oxide over the plurality of first fins, the plurality of second fins, and the top surfaces of the plurality of STI regions using an atomic layer deposition (ALD) process, wherein material of the oxide comprises a second material layer that is different than the first material layer; after forming the oxide, performing a first post-treatment process, the first post-treatment process comprising an ultraviolet (UV) light treatment process in ambient O 3 , wherein the UV light treatment process is performed at a temperature of from about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, or for a time period of from about 1 minute to about 10 minutes; and after the first post-treatment process, performing a second post-treatment process, the second post-treatment process comprising an oxygen-containing post-treatment process, the second post-treatment process different than the first post-treatment process, where the second post-treatment is annealing in ambient O2, the anneal process is performed at a temperature between 400 and 600 degrees Celsius or at a pressure between 5 and 20 atmospheres.
11. A method of manufacturing a fin field effect (FinFET) semiconductor device, comprising: patterning isolation regions over a substrate with a pattern for a first fin and a second fin; forming the first fin by epitaxially growing the first fin in a first region of the substrate within the pattern formed in the isolation regions; forming the second fin by epitaxially growing the second fin in a second region of the substrate within the pattern formed in the isolation regions, the second fin comprising a material different from a material of the substrate; depositing an oxide layer over the first fin and the second fin at a temperature of about 200 degrees C. to about 400 degrees C., the oxide layer deposited with an atomic layer deposition (ALD) process; first treating the oxide layer using an O 2 plasma treatment to form a first treated oxide layer; second treating the first treated oxide layer to form a second treated oxide layer having an improved quality oxide relative the first treated oxide layer, wherein the second treating comprises performing a ultraviolet (UV) light treatment process in ambient O 3 at a temperature of about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, and for a time period of from about 1 minute to about 10 minutes; disposing a gate dielectric layer over the second treated oxide layer; and disposing a gate material over the gate dielectric layer of the FinFET semiconductor device.
A method for manufacturing a FinFET semiconductor device: First, pattern isolation regions on a substrate, creating areas for a first fin and a second fin. Then, grow the first fin epitaxially within its designated area inside the isolation region pattern. Next, grow the second fin epitaxially in its area within the isolation pattern, using a material different from the substrate. Deposit an oxide layer over both fins using atomic layer deposition (ALD) at a temperature between 200 and 400 degrees Celsius. Treat the oxide layer with an oxygen plasma to create a first treated oxide layer. Then, treat the first treated oxide layer again, improving its quality, using ultraviolet (UV) light in an ozone atmosphere at a temperature between 300 and 450 degrees Celsius, a pressure between 4 and 20 Torr, and for 1 to 10 minutes. Finally, deposit a gate dielectric layer over the second treated oxide and a gate material over the gate dielectric.
12. The method according to claim 11 , wherein second treating comprises an anneal process in an O 2 ambient environment at a temperature less than about 600 degrees C.
This FinFET manufacturing process, involving patterning isolation regions over a substrate with a pattern for a first fin and a second fin; forming the first fin by epitaxially growing the first fin in a first region of the substrate within the pattern formed in the isolation regions; forming the second fin by epitaxially growing the second fin in a second region of the substrate within the pattern formed in the isolation regions, the second fin comprising a material different from a material of the substrate; depositing an oxide layer over the first fin and the second fin at a temperature of about 200 degrees C. to about 400 degrees C., the oxide layer deposited with an atomic layer deposition (ALD) process; first treating the oxide layer using an O 2 plasma treatment to form a first treated oxide layer; second treating the first treated oxide layer to form a second treated oxide layer having an improved quality oxide relative the first treated oxide layer, wherein the second treating comprises performing a ultraviolet (UV) light treatment process in ambient O 3 at a temperature of about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, and for a time period of from about 1 minute to about 10 minutes; disposing a gate dielectric layer over the second treated oxide layer; and disposing a gate material over the gate dielectric layer of the FinFET semiconductor device, includes an annealing process as the second treatment in an oxygen environment at a temperature less than 600 degrees Celsius.
13. The method according to claim 11 , wherein forming the first fin and forming the second fin comprises: etching the substrate to form the first fin and the second fin; masking the first fin; and introducing a substance to alter the material of the second fin to form the material different from the material of the substrate.
In this FinFET fabrication approach, involving patterning isolation regions over a substrate with a pattern for a first fin and a second fin; forming the first fin by epitaxially growing the first fin in a first region of the substrate within the pattern formed in the isolation regions; forming the second fin by epitaxially growing the second fin in a second region of the substrate within the pattern formed in the isolation regions, the second fin comprising a material different from a material of the substrate; depositing an oxide layer over the first fin and the second fin at a temperature of about 200 degrees C. to about 400 degrees C., the oxide layer deposited with an atomic layer deposition (ALD) process; first treating the oxide layer using an O 2 plasma treatment to form a first treated oxide layer; second treating the first treated oxide layer to form a second treated oxide layer having an improved quality oxide relative the first treated oxide layer, wherein the second treating comprises performing a ultraviolet (UV) light treatment process in ambient O 3 at a temperature of about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, and for a time period of from about 1 minute to about 10 minutes; disposing a gate dielectric layer over the second treated oxide layer; and disposing a gate material over the gate dielectric layer of the FinFET semiconductor device, the first and second fins are formed by first etching the substrate. Then, the first fin is masked off. A substance is then introduced to change the material of the second fin, resulting in a different material from the substrate.
14. The method according to claim 1 , wherein the in-situ O2 plasma treatment comprises a temperature of about 200 degree C. to about 400 degrees C.
The method where a first fin and a second fin are formed on a substrate, the first fin is masked while a substance alters the second fin's material making it different from the substrate; after forming the fins, an isolation region is created between them; a SiO2 layer is deposited over the fins and the isolation region using plasma-enhanced atomic layer deposition (PE-ALD) process at a power of from about 10 Watts to about 500 Watts and at a temperature of from about 200 degrees C. to about 400 degrees C.; followed by an in-situ O2 plasma treatment at a temperature of about 600 degrees C. or less; and finally an anneal process, the annealed SiO 2 layer forming a gate dielectric of the FinFET semiconductor device, the in-situ O2 plasma treatment is performed at a temperature between 200 and 400 degrees Celsius.
15. The method according to claim 1 , wherein a width of the second fin after post-treating the SiO 2 layer is the same as the width of the second fin before post-treating the SiO 2 layer.
The method for creating FinFET devices, including forming a first fin and a second fin on a substrate, masking the first fin while a substance alters the material of the second fin to be different than the substrate material, forming an isolation region between the fins, depositing SiO2 using PE-ALD at 10-500W and 200-400C, performing in-situ O2 plasma treatment at <=600C, and annealing to form the gate dielectric, ensures that the width of the second fin remains unchanged by the post-treatment process. The second fin width after post-treating the SiO2 layer remains the same as the width before post-treating the SiO2 layer.
16. The method according to claim 1 , wherein the altered material of the second fin comprises SiGe, and wherein the SiO 2 layer is free of SiGe.
The method including: forming first/second fins on a substrate (first fin same material, second fin altered to different material), masking the first fin while a substance alters the second fin's material, forming an isolation region, depositing SiO2 using PE-ALD at 10-500W and 200-400C, performing in-situ O2 plasma treatment at <=600C, and annealing to form the gate dielectric, specifies that the altered material of the second fin is Silicon Germanium (SiGe), and the deposited silicon dioxide (SiO2) layer contains no Silicon Germanium (SiGe).
17. The method according to claim 7 , wherein widths of the second fins after performing a second post-treatment process is the same as the widths of the second fins before performing a second post-treatment process.
This method of FinFET fabrication, forming first and second fins (different materials) with STI regions, depositing an oxide layer, performing a UV/O3 post-treatment followed by an oxygen-containing post-treatment, ensures that the widths of the second fins remain unchanged during the second post-treatment process. In other words, the widths of the second fins are the same after and before the second post-treatment.
18. The method according to claim 7 , further comprising: depositing a gate dielectric over the oxide; and depositing a gate material over the gate dielectric.
Building on the FinFET manufacturing method of forming a plurality of first fins over a substrate, the plurality of first fins comprising a same material as a material of the substrate; forming a plurality of second fins over the substrate, the plurality of second fins comprising a different material than the material of the substrate; forming a plurality of shallow trench isolation (STI) regions between the plurality of first fins and the plurality of second fins, wherein top surfaces of the plurality of STI regions are recessed below top surfaces of the plurality of first fins and the plurality of second fins, the plurality of STI regions comprising a first material layer; forming an oxide over the plurality of first fins, the plurality of second fins, and the top surfaces of the plurality of STI regions using an atomic layer deposition (ALD) process, wherein material of the oxide comprises a second material layer that is different than the first material layer; after forming the oxide, performing a first post-treatment process, the first post-treatment process comprising an ultraviolet (UV) light treatment process in ambient O 3 , wherein the UV light treatment process is performed at a temperature of from about 300 degrees C. to about 450 degrees C., at a pressure of from about 4 Torr to about 20 Torr, or for a time period of from about 1 minute to about 10 minutes; and after the first post-treatment process, performing a second post-treatment process, the second post-treatment process comprising an oxygen-containing post-treatment process, the second post-treatment process different than the first post-treatment process, it further involves depositing a gate dielectric over the oxide layer and depositing a gate material over the gate dielectric.
19. The method according to claim 7 , wherein performing the second post-treatment process further comprises: an anneal process in ambient O 2 .
This FinFET fabrication method, comprising forming first and second fins of differing materials, forming shallow trench isolation (STI) regions, depositing an oxide layer, performing a first post-treatment using UV light in ozone, and performing a second oxygen-containing post-treatment, where performing the second post-treatment process further comprises annealing in ambient O2.
20. The method according to claim 11 , wherein a width of the second fin after the second treating the first treated oxide layer is the same as the width of the second fin before the second treating the first treated oxide layer.
The FinFET manufacturing method of patterning isolation regions; forming first/second fins (different materials) by epitaxial growth; depositing an oxide layer using ALD at 200-400C; first treating with O2 plasma; second treating with UV/O3 at 300-450C, 4-20 Torr, 1-10 min; disposing a gate dielectric layer; and disposing a gate material, maintains the width of the second fin. The width of the second fin after the second treatment is the same as the width before the second treatment.
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March 6, 2014
November 14, 2017
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