Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.
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1. An apparatus comprising: a pair of bit lines coupled to a plurality of memory cells; a sense amplifier circuit coupled to the pair of bit lines; a pair of differential data lines coupled to the sense amplifier; a single-ended data line; a first transistor coupled between a first power line supplied with a first voltage and one of the pair of differential data lines and coupled to the other of the pair of differential data lines at a control node thereof; and a second transistor coupled between a second power line supplied with a second voltage different from the first voltage and the one of the pair of differential data lines and coupled to the single-ended data line at a control node thereof.
A memory device includes a pair of bit lines connected to memory cells and a sense amplifier to read data from the bit lines. The sense amplifier outputs to a pair of differential data lines. A single-ended data line is included for data transfer. A first transistor connects one of the differential data lines to a first voltage source. The gate of the first transistor is connected to the other differential data line. A second transistor connects the same differential data line to a second voltage source (different from the first). The gate of the second transistor is connected to the single-ended data line.
2. The apparatus of claim 1 , further comprising a third transistor between the other of the pair of differential data lines and the single-ended data line and a fourth transistor between the second transistor and the second power line.
The memory device from the previous description also has a third transistor connected between the other differential data line and the single-ended data line. A fourth transistor is connected between the second transistor (which connects a differential data line to a second voltage source, with its gate connected to the single-ended data line) and the second voltage source.
3. The apparatus of claim 2 , wherein the third transistor and the fourth transistor are configured to be turned on in a write operation.
In the memory device with the additional transistors (a third transistor between the other differential data line and the single-ended data line, and a fourth transistor between the second transistor and the second power line), the third and fourth transistors are turned on during a write operation to write data to the memory cells.
4. The apparatus of claim 1 ., further comprising a precharge circuit configured to precharge the pair of differential data lines to the first voltage.
The memory device from the first description, containing differential data lines, a single-ended data line, and two transistors forming a bridge between these lines, also incorporates a precharge circuit. This precharge circuit sets both differential data lines to the first voltage level before a read or write operation to ensure a proper starting point for sensing data.
5. The apparatus of claim 1 , further comprising a third transistor coupled between the first power line and the other of the pair of differential data lines and coupled to the one of the pair of differential data lines at a control node thereof.
In addition to the components described previously (differential data lines, a single-ended data line, and two transistors), a third transistor is included. This third transistor is connected between the first voltage source and the other differential data line. The gate of this third transistor is connected to the one differential data line. It forms a complementary connection to the first transistor which is coupled between a first power line supplied with a first voltage and one of the pair of differential data lines and coupled to the other of the pair of differential data lines at a control node thereof.
6. The apparatus of claim 2 , wherein the third transistor is an N-channel transistor and the first voltage is supplied at the control node of the third transistor as the control signal in a write operation.
In the memory device from Claim 2 (which includes the differential and single ended lines with a first and second transistor as well as a third transistor between the other of the pair of differential data lines and the single-ended data line and a fourth transistor between the second transistor and the second power line), the third transistor is an N-channel type. During a write operation, the first voltage is applied to the gate of the third transistor to activate it, facilitating the write process.
7. An apparatus comprising: a pair of bit lines coupled to a plurality of memory cells; a sense amplifier circuit coupled to the pair of bit lines; a pair of differential data lines coupled to the sense amplifier; a single-ended data line; and a first transistor coupled between one of the pair of differential data lines and the single-ended data line, the first transistor receiving a control signal at a control node thereof; and a second transistor coupled between a first power line supplied with a first voltage and the single-ended data line and coupled to the other of the pair of differential data lines at a control node thereof.
The memory device has a pair of bit lines connected to memory cells and a sense amplifier to read the data. The sense amplifier outputs to a pair of differential data lines. A single-ended data line transfers data. A first transistor connects one of the differential data lines to the single-ended data line and is controlled by a control signal at its gate. A second transistor connects the single-ended data line to a first voltage source, with its gate connected to the other differential data line.
8. The apparatus of claim 7 , further comprising a third transistor coupled between the first power line and the second transistor.
The memory device from the previous description (containing differential and single ended lines, and two transistors) further has a third transistor. This third transistor connects the first voltage source to the second transistor (which is coupled between a first power line supplied with a first voltage and the single-ended data line and coupled to the other of the pair of differential data lines at a control node thereof).
9. The apparatus of claim 8 , wherein the third transistor is configured to he turned on in a read operation.
The memory device, as defined previously (containing the third transistor connected between the first voltage source and the second transistor), has the third transistor turned on during a read operation to enable data to be sensed by the amplifier circuit.
10. The apparatus of claim 9 wherein the first transistor is configured to be turned on in the write operation.
The memory device, including the third transistor configured to turn on during a read operation, is configured so that the first transistor (coupled between one of the pair of differential data lines and the single-ended data line) is turned on during a write operation to allow data to be written to the memory cells.
11. The apparatus of claim 7 , further comprising a precharge circuit configured to precharge the pair of differential data lines to the first voltage.
In the memory device consisting of differential data lines, a single-ended data line, and two transistors, a precharge circuit precharges the pair of differential data lines to the first voltage before the read/write operation, similar to Claim 4.
12. The apparatus of claim 8 , further comprising: a fourth transistor coupled between a second power line supplied with a second voltage different from the first voltage and the other of the pair of differential data lines and coupled to the one of the pair of differential data lines at a control node thereof; and a fifth transistor coupled between the first power line and the other of the pair of differential data lines and coupled to the single-ended data line at a control node thereof.
In the device from Claim 8 which includes the differential and single ended lines, and two transistors and a third transistor connected between the first voltage source and the second transistor, a fourth transistor connects a second voltage source (different from the first) to the other differential data line. Its gate connects to the one differential data line. A fifth transistor connects the first voltage source to the other differential data line, with the gate connected to the single-ended data line.
13. The apparatus of claim 12 , further comprising a sixth transistor coupled between the first power line and the fifth transistor, the sixth transistor receiving an additional control signal at a control node thereof.
Building upon the previous device (containing the fourth and fifth transistors), a sixth transistor is added. This sixth transistor connects the first voltage source to the fifth transistor, and it receives a separate control signal at its gate to control its on/off state.
14. The apparatus of claim 13 , wherein each of the first and sixth transistors is configured to be turned on in a mite operation and the third transistor is configured to be turned on in a read operation.
In the architecture that has the first and sixth transistors configurable, they are turned on for writing. The third transistor, on the other hand, is turned on during reading to enable the read functionality.
15. An apparatus comprising: a pair of differential data lines; a single-ended data line; a first transistor coupled between a first power line supplied with a first voltage and one of the pair of differential data lines and coupled to the other of the pair of differential data lines at a control node thereof; and a second transistor coupled between a second power line supplied with a second voltage different from the first voltage and the one of the pair of differential data lines and coupled to the single-ended data line at a control node thereof. a third transistor coupled between the other of the pair of differential data lines and the single-ended data line, the third transistor receiving a control signal at a control node thereof; and a fourth transistor coupled between the second power line and the single-ended data line and coupled to the one of the pair of differential data lines at a control node thereof.
A circuit includes differential data lines and a single-ended data line. A first transistor connects a first voltage source to one differential data line, with its gate connected to the other differential data line. A second transistor connects a second voltage source to the same differential data line, with its gate connected to the single-ended data line. A third transistor connects the other differential data line to the single-ended data line and receives a control signal at its gate. A fourth transistor connects the second voltage source to the single-ended data line and its gate is connected to one of the differential data lines.
16. The apparatus of claim 15 , wherein the first transistor is different in conductivity type from each of the second, third and fourth transistors.
In the circuit defined above (differential and single ended data lines connected to transistors), the first transistor has a different conductivity type (e.g., PMOS) than the second, third, and fourth transistors (e.g., NMOS). This means it operates in the opposite way - a high gate voltage turns off a PMOS transistor, while it turns on an NMOS transistor.
17. The apparatus of claim 15 , further comprising a fifth transistor coupled between the first power line and the other of the pair of differential data lines and coupled to the one of the pair of differential data lines at a control node thereof.
A prior description of a device with differential and single-ended data lines and transistors (as well as the other transistors previously mentioned) has a fifth transistor connected between the first voltage source and the other differential data line. Its gate is connected to the one differential data line forming a complementary connection between the two differential lines.
18. The apparatus of claim 15 , further comprising: a sense amplifier circuit configured to amplify a voltage of the pair of differential data lines; a driver circuit configured to drive the single-ended data line; a fifth transistor coupled between the second power line and the fourth transistor, the fifth transistor configured to be turned on when the sense amplifier circuit amplifies the voltage of the pair of differential data lines; and a sixth transistor coupled between the second power line and the second transistor, the sixth transistor configured to be turned on when the driver circuit drives the single-ended data line.
The memory device includes the components from claim 15 (differential and single-ended data lines, four transistors, and control signals). Additionally, it includes a sense amplifier to amplify the voltage difference between the differential data lines, and a driver circuit to drive the single-ended data line. A fifth transistor is connected between the second voltage source and the fourth transistor, turned on when the sense amplifier amplifies the voltage. A sixth transistor is connected between the second voltage source and the second transistor and is turned on when the driver circuit drives the single-ended data line.
19. The apparatus of claim 15 , further comprising a precharge circuit configured to precharge the pair of differential data lines to the first voltage.
A memory device composed of differential data lines, a single-ended data line and transistors, also contains a precharge circuit. The precharge circuit is configured to precharge the differential data lines to a first voltage before the read or write operations begin to improve sensing performance.
20. The apparatus of claim 18 , further comprising a seventh transistor coupled between the first power line and the other of the pair of differential data lines and coupled to the one of the pair of differential data lines at a control node thereof; wherein the first and seventh transistors are first conductivity type transistors and the second, third, fourth, fifth and sixth transistors are second conductivity type transistors.
Building upon the previous definition of the circuit, a seventh transistor is added between the first voltage source and the other differential data line, with the gate connected to the one differential data line. The first and seventh transistors are of a first conductivity type (like PMOS), while the second, third, fourth, fifth, and sixth transistors are of a second conductivity type (like NMOS). This configuration enables the circuit to operate by inverting voltage states.
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April 21, 2017
November 21, 2017
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