A latch circuit may be provided. The latch circuit may include a plurality of latches configured to store and output data through input/output signal lines according to input/output control signals. Latches coupled with input/output signal lines of same orders among the plurality of latches may be disposed by being distributed by orders of the input/output control signals. A plurality of pipe latches may be configured by latches which are inputted with input/output control signals of same orders, among the latches disposed by being distributed.
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1. A latch circuit comprising: a plurality of pipe latches configured to store and output data through input/output signal lines according to input/output control signals, wherein the plurality of pipe latches are directly connected to with same input/output signal lines, and wherein the plurality of pipe latches are inputted with signals of different orders among the input/output control signals.
A latch circuit has multiple "pipe latches" that store and output data based on input/output control signals. These pipe latches connect directly to the same input/output signal lines. Each pipe latch receives a different order of the input/output control signals. This allows the circuit to process data in a pipelined manner, improving throughput by allowing different stages of processing to occur simultaneously on different data elements.
2. The latch circuit according to claim 1 , wherein latches which configure the plurality of pipe latches are coupled with input/output signal lines of different orders among the input/output signal lines.
The latch circuit as described with multiple pipe latches connected to the same input/output signal lines, where each pipe latch receives a different order of the input/output control signals, is further defined such that the latches forming the pipe latches connect to different input/output signal lines. This arrangement allows for parallel data processing, improving the overall speed of the latch circuit.
3. The latch circuit according to claim 1 , further comprising: an output selection block configured to primarily multiplex data outputted from the plurality of pipe latches, according to first order of output control signals among the input/output control signals, and output resultant data, and secondarily multiplex primarily multiplexed data according to a second order of the output control signals and output resultant data.
The latch circuit as described with multiple pipe latches connected to the same input/output signal lines, where each pipe latch receives a different order of the input/output control signals, further contains an output selection block. This block first multiplexes data coming from the pipe latches, based on the first order of output control signals. It then multiplexes the result again based on the second order of the output control signals. This enables selecting specific data outputs from the pipe latches in a controlled manner, based on the order of the control signals.
4. The latch circuit according to claim 3 , wherein the output selection block comprises: a first multiplexer configured to select and output, according to a first selection control signal, one among output data of latches from which data are outputted according to some among even output control signals and output data of latches from which data are outputted according to remainders among the even output control signals; a second multiplexer configured to select and output, according to a second selection control signal, one among output data of latches from which data are outputted according to some among odd output control signals and output data of latches from which data are outputted according to remainders among the odd output control signals; and a third multiplexer configured to generate an output signal by selecting one between an output signal of the first multiplexer and an output signal of the second multiplexer according to a third selection control signal.
The latch circuit, including pipe latches and an output selection block that multiplexes data based on the order of output control signals, is further defined such that the output selection block includes three multiplexers. The first multiplexer selects between data from latches outputting based on even output control signals. The second multiplexer selects between data from latches outputting based on odd output control signals. The third multiplexer then selects the final output from either the first or second multiplexer, providing a flexible output selection mechanism.
5. A latch circuit comprising: a plurality of pipe latches configured to store and output data through input/output signal lines according to input/output control signals, wherein some of the plurality of pipe latches are directly connected to signal lines of even orders among the input/output signal lines, and remainders of the plurality of pipe latches are directly connected to signal lines of odd orders among the input/output signal lines, and wherein the some of the plurality of pipe latches are inputted with signals of different orders among the input/output control signals.
A latch circuit includes multiple "pipe latches" that store and output data based on input/output control signals. Some of these pipe latches connect directly to signal lines of even orders among the input/output signal lines. The remaining pipe latches connect directly to signal lines of odd orders among the input/output signal lines. Each pipe latch receives signals of different orders among the input/output control signals. This design separates even and odd signal lines, potentially reducing interference and improving signal integrity.
6. The latch circuit according to claim 5 , wherein latches which configure the plurality of pipe latches are coupled with input/output signal lines of different orders among the input/output signal lines.
The latch circuit as described with multiple pipe latches where even and odd signal lines are separated, and each pipe latch receives different input/output control signals, is further defined such that the latches forming the pipe latches are coupled to different input/output signal lines. This promotes parallel data processing and improves overall circuit performance.
7. The latch circuit according to claim 5 , further comprising: an output selection block configured to primarily multiplex data outputted from the plurality of pipe latches, according to an order of output control signals among the input/output control signals, and output resultant data, and secondarily multiplex primarily multiplexed data according to an order of the input/output signal lines and output resultant data.
The latch circuit as described with multiple pipe latches where even and odd signal lines are separated, and each pipe latch receives different input/output control signals, further contains an output selection block. This block first multiplexes data coming from the pipe latches, based on the order of output control signals. It then multiplexes the result again, this time based on the order of the input/output signal lines. This configuration enables more flexible output selection by considering both control signal order and signal line order.
8. The latch circuit according to claim 7 , wherein the output selection block comprises: a first multiplexer configured to select and output, according to a first selection control signal, one among output data of latches from which data are outputted according to some among even output control signals and output data of latches from which data are outputted according to remainders among the even output control signals; a second multiplexer configured to select and output, according to a second selection control signal, one among output data of latches from which data are outputted according to some among odd output control signals and output data of latches from which data are outputted according to remainders among the odd output control signals; and a third multiplexer configured to generate an output signal by selecting one between an output signal of the first multiplexer and an output signal of the second multiplexer according to a third selection control signal.
The latch circuit, including pipe latches and an output selection block that multiplexes data based on both control signal order and signal line order, is further defined such that the output selection block includes three multiplexers. The first multiplexer selects between data from latches outputting based on even output control signals. The second multiplexer selects between data from latches outputting based on odd output control signals. The third multiplexer then selects the final output from either the first or second multiplexer, offering a versatile output selection mechanism for the pipelined data.
9. A semiconductor apparatus comprising: a semiconductor memory in which a plurality of memory chips are stacked, at least one among the memory chips comprising: a through electrode region where a plurality of through electrodes are disposed, and a latch circuit disposed in the through electrode region, wherein the latch circuit comprises a plurality of pipe latches, and the plurality of pipe latches are directly connected to input/output signal lines, and wherein the plurality of pipe latches are inputted with signals of different orders among input/output control signals.
A semiconductor apparatus includes a semiconductor memory with stacked memory chips. At least one of these chips has a "through electrode region" containing multiple through electrodes and a latch circuit. The latch circuit contains multiple pipe latches that connect directly to input/output signal lines, and each of these pipe latches receives input/output control signals of different orders. The apparatus utilizes the through electrodes for vertical signal transmission between stacked memory chips. The pipe latches facilitate high-speed data transfer.
10. The semiconductor apparatus according to claim 9 , wherein latches which configure the plurality of pipe latches are coupled with signal lines of different orders among the input/output signal lines.
The semiconductor apparatus with stacked memory chips, through electrodes, and a latch circuit containing pipe latches where each of these pipe latches receives input/output control signals of different orders, is further defined such that the latches forming the pipe latches are coupled with signal lines of different orders. This arrangement helps optimize parallel data processing.
11. The semiconductor apparatus according to claim 9 , wherein the latch circuit comprises an output selection block configured to primarily multiplex data outputted from the plurality of pipe latches, according to first order of output control signals among the input/output control signals, and output resultant data, and secondarily multiplex primarily multiplexed data according to a second order of the output control signals and output resultant data.
The semiconductor apparatus with stacked memory chips, through electrodes, and a latch circuit containing pipe latches where each of these pipe latches receives input/output control signals of different orders, further includes an output selection block. This block primarily multiplexes the data outputted from the pipe latches based on the first order of the output control signals, then secondarily multiplexes the primarily multiplexed data according to a second order of the output control signals.
12. The semiconductor apparatus according to claim 11 , wherein the output selection block comprises: a first multiplexer configured to select and output, according to a first selection control signal, one among output data of latches from which data are outputted according to some among even output control signals and output data of latches from which data are outputted according to remainders among the even output control signals; a second multiplexer configured to select and output, according to a second selection control signal, one among output data of latches from which data are outputted according to some among odd output control signals and output data of latches from which data are outputted according to remainders among the odd output control signals; and a third multiplexer configured to generate an output signal by selecting one between an output signal of the first multiplexer and an output signal of the second multiplexer according to a third selection control signal.
The semiconductor apparatus, including stacked memory chips, through electrodes, pipe latches, and an output selection block, is further defined such that the output selection block includes three multiplexers. The first multiplexer selects between data from latches outputting based on even output control signals. The second multiplexer selects between data from latches outputting based on odd output control signals. The third multiplexer selects the final output from either the first or second multiplexer.
13. The semiconductor apparatus according to claim 9 , wherein some of the plurality of pipe latches are coupled with signal lines of even orders among the input/output signal lines in common, and remainders of the plurality of pipe latches are coupled with signal lines of odd orders among the input/output signal lines in common, and wherein the some of the plurality of pipe latches are inputted with signals of different orders among the input/output control signals.
A semiconductor apparatus includes stacked memory chips. At least one of the chips has pipe latches. Some of these pipe latches are coupled in common with signal lines of even orders among the input/output signal lines, while the remaining pipe latches are coupled in common with signal lines of odd orders among the input/output signal lines. The pipe latches receive signals of different orders among the input/output control signals. This design aims at optimized data transfer between stacked chips.
14. The semiconductor apparatus according to claim 9 , wherein the latch circuit comprises an output selection block configured to primarily multiplex data outputted from the plurality of pipe latches, according to an order of output control signals among the input/output control signals, and output resultant data, and secondarily multiplex primarily multiplexed data according to an order of the input/output signal lines and output resultant data.
The semiconductor apparatus with stacked memory chips, including pipe latches connected to signal lines, and each of these pipe latches receives input/output control signals of different orders, is further defined by an output selection block. This block first multiplexes data from the pipe latches based on the order of the output control signals and then multiplexes the primarily multiplexed data based on the order of the input/output signal lines. This creates flexible output selection.
15. The semiconductor apparatus according to claim 14 , wherein the output selection block comprises: a first multiplexer configured to select and output, according to a first selection control signal, one among output data of latches from which data are outputted according to some among even output control signals and output data of latches from which data are outputted according to remainders among the even output control signals; a second multiplexer configured to select and output, according to a second selection control signal, one among output data of latches from which data are outputted according to some among odd output control signals and output data of latches from which data are outputted according to remainders among the odd output control signals; and a third multiplexer configured to generate an output signal by selecting one between an output signal of the first multiplexer and an output signal of the second multiplexer according to a third selection control signal.
The semiconductor apparatus, including stacked memory chips, pipe latches connected to signal lines, output control signals of different orders, and a flexible output selection, is further defined such that the output selection block includes three multiplexers. The first multiplexer selects between data from latches outputting based on even output control signals. The second multiplexer selects between data from latches outputting based on odd output control signals. The third multiplexer selects the final output from either the first or second multiplexer.
16. The semiconductor apparatus according to claim 9 , wherein the plurality of memory chips include a base die and core dies stacked over the base die, and wherein the latch circuit is disposed in the through electrode region of a core die.
In the semiconductor apparatus with stacked memory chips, the chips consist of a base die and core dies stacked on top of it. The latch circuit is located in the through electrode region of one of the core dies. This positions the latch circuit close to the through-silicon vias (TSVs) used for vertical inter-chip communication, minimizing signal path lengths and improving data transfer speeds.
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May 12, 2016
November 28, 2017
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