Imagine your toy car. It has a tiny engine, right? But what if you wanted to put a super-duper engine in it that makes it go really, really fast, AND you want the car to be even smaller? That's a tricky problem!
Our brainy scientists and engineers came up with a super clever idea, like a secret blueprint, called the "Semiconductor Package and Fabricating Method Thereof" patent. 🤯
Think of the 'semiconductor package' as the special box where the tiny engine (which is actually a microchip, the brain of your phone or computer) lives. Inside this box, there are super-duper tiny roads (called 'redistribution structures') that help the engine parts talk to each other really fast.
Before this invention, these roads were a bit thick and sometimes bumpy, making the box a bit chunky. But this new secret blueprint shows how to build these roads super-thin and super-close together, like making a highway with many more lanes in the same space, but without making the whole highway bigger!
So, what does this mean for you, a five-year-old?
It's like magic, but it's really clever engineering that helps make all our cool electronic toys and gadgets better!
The patent titled "Semiconductor Package and Fabricating Method Thereof" (US-9852976) introduces a groundbreaking approach to designing and manufacturing semiconductor devices, specifically focusing on advanced packaging solutions. The core innovation lies in its ability to create exceptionally thin, fine-pitch redistribution structures within semiconductor packages. These structures are critical for increasing the density of interconnections—the tiny pathways that carry electrical signals within a microchip—without expanding the overall physical size of the package.
The primary problem this invention solves is the limitation of conventional semiconductor packaging methods in accommodating the ever-growing demand for miniaturization and enhanced performance. As chips become more complex and require more input/output (I/O) connections, traditional redistribution layers become too thick or imprecise, hindering further device shrinkage and often leading to signal integrity issues. This patent provides a robust solution to overcome these physical and manufacturing constraints.
Technically, the approach detailed in this patent involves novel designs for semiconductor package structures that integrate these thin, high-density redistribution layers. The fabricating method described ensures precise control over the deposition and patterning of conductive traces and dielectric layers, allowing for ultra-fine line widths and spaces. This meticulous control results in superior electrical performance, reduced parasitic effects, and improved mechanical reliability, even in incredibly compact forms.
The business value and applications are profound. This technology enables the production of thinner, lighter, and more powerful electronic devices across various sectors, including mobile computing, wearable technology, artificial intelligence accelerators, and high-performance computing. It offers a significant competitive advantage to manufacturers by facilitating higher integration density, potentially reducing manufacturing costs through improved yields, and accelerating the development of next-generation products.
The market opportunity for this innovation is substantial, as it addresses a fundamental need in an industry constantly pushing the boundaries of miniaturization and performance. By providing a reliable method for advanced packaging, this patent positions itself as an enabler for future technological advancements, ensuring that electronic devices can continue to evolve in form factor and capability.
Imagine you're trying to build a super-fast, super-small computer, like the brain of a new smartphone or a tiny sensor for a smart home. Inside this computer's 'brain' (which is called a microchip or semiconductor device), there are millions of tiny electrical roads, or wires, that carry information. As we want these devices to get smaller and more powerful, we need to pack even more of these roads into a tiny space, making them incredibly thin and close together – what engineers call 'fine-pitch'.
The big problem is that with older ways of building these chips, making these roads so thin and close together becomes incredibly difficult. It's like trying to draw a million perfect, hair-thin lines without any of them touching or breaking. This leads to bigger, thicker chips than we want, or chips that don't work reliably, costing manufacturers a lot of money and slowing down innovation. Existing solutions often hit physical limits, making it hard to create devices that are both high-performing and sleek.
The patent "Semiconductor Package and Fabricating Method Thereof" offers a brilliant new recipe for building these tiny chips. Instead of just trying to make existing roads thinner, this innovation redesigns the entire 'package' or casing that holds the chip, and the way those internal roads are constructed. Think of it like this:
Instead of a single, slightly thick layer of roads, this new approach uses multiple, super-thin layers, stacked perfectly on top of each other. Each layer has incredibly precise, hair-thin conductive paths (the 'fine-pitch redistribution structures'). The method describes how to deposit special materials and carve out these tiny roads with extreme accuracy, layer by layer, almost like 3D printing, but on a microscopic scale. This meticulous process ensures that even though the roads are incredibly close, they don't interfere with each other, and the entire stack remains very thin.
It's like having a multi-story highway system inside your chip. Each story is ultra-flat and perfectly engineered, allowing for a massive amount of traffic (electrical signals) to flow efficiently without congestion, all within a compact skyscraper. This conceptual shift allows for greater connectivity and functionality to be integrated into a much smaller volume than previously possible, without sacrificing performance.
This technology matters because it directly enables the next generation of electronic devices that consumers and businesses demand. For consumers, it means: thinner, lighter smartphones and laptops; more comfortable and feature-rich wearables; and faster, more responsive smart home devices. For businesses, it translates into:
The "Semiconductor Package and Fabricating Method Thereof" is a foundational technology. Looking ahead, we can expect to see its principles integrated into a wide array of high-performance and ultra-compact devices. It will be crucial for the advancement of Artificial Intelligence (AI) hardware, enabling more powerful AI processing in smaller form factors. It will also drive innovation in the Internet of Things (IoT), allowing for tiny, energy-efficient sensors and communication modules. As industries continue to demand more integrated and miniaturized electronics, the adoption of this approach will become increasingly widespread, shaping product roadmaps for the next decade and beyond. This patent isn't just an incremental step; it's a strategic leap forward.
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
The patent "Semiconductor Package and Fabricating Method Thereof" (US-9852976) details a sophisticated solution for advanced semiconductor packaging, specifically addressing the critical need for thin, fine-pitch redistribution structures. This technical analysis delves into the architectural and methodological innovations presented by this patent.
Technical Architecture of the Semiconductor Package At its core, this patent describes a semiconductor package structure designed to integrate a semiconductor die with high-density, fine-pitch redistribution layers (RDLs). The architecture typically comprises:
The structural innovation allows for a high density of interconnections within a minimal vertical stack height, directly contributing to overall package thinness and improved electrical performance by reducing parasitic effects associated with longer or less precise routing.
Implementation Details and Fabrication Method The fabricating method thereof is crucial to achieving the described architecture. It outlines a series of precise processing steps, often performed at the wafer level (Wafer-Level Packaging – WLP) or fan-out wafer-level packaging (FOWLP) to maximize efficiency and precision:
Algorithm Specifics (Implicit) While no explicit algorithms are detailed, the method implies highly precise computational models for:
Integration Patterns and Performance Characteristics This technology is highly compatible with advanced packaging integration patterns such as 2.5D and 3D ICs, where interposers or through-silicon vias (TSVs) require extremely fine-pitch connectivity. The performance characteristics enabled are superior:
This patent provides a critical technical foundation for the next generation of high-performance, compact electronic devices, offering a pathway to overcome the physical limitations of current semiconductor packaging.
The patent "Semiconductor Package and Fabricating Method Thereof" (US-9852976) represents a significant advancement in semiconductor packaging, with profound implications for various industries and substantial market opportunities. This innovation addresses a core bottleneck in modern electronics manufacturing: the ability to create smaller, more powerful, and cost-effective microchips.
Market Opportunity Size: The global semiconductor packaging market is a multi-billion dollar industry, continuously growing due to the pervasive demand for electronics. Within this, advanced packaging, specifically solutions enabling miniaturization and high-density integration, is the fastest-growing segment. This patent directly targets this high-growth area, which is critical for sectors like mobile communication, IoT, AI/ML hardware, automotive electronics, and high-performance computing. The addressable market for this technology is therefore immense, encompassing virtually all manufacturers of advanced semiconductor devices. As devices demand finer pitches and thinner profiles, the market for solutions like this will only expand.
Competitive Advantages: This technology offers several compelling competitive advantages:
Revenue Potential: Revenue can be generated through multiple avenues:
Business Models: Potential business models include:
Strategic Positioning: Companies leveraging this patent can strategically position themselves as leaders in advanced packaging, high-performance computing components, or miniaturized electronics. This technology allows for greater design flexibility, enabling new product categories and enhancing existing ones, thereby securing a strong foothold in the value chain.
ROI Projections: The ROI for investing in or licensing this technology can be substantial. Reduced manufacturing defects, increased yields, and the ability to command higher prices for superior products contribute to improved profit margins. Furthermore, the strategic advantage of enabling next-generation devices can lead to significant market share gains and long-term business growth. Early adopters could see a rapid return on investment through product differentiation and market leadership in key technology segments.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device comprising: a first redistribution structure comprising: a first dielectric layer comprising a first dielectric material; a first conductive trace embedded in the first dielectric layer and comprising: a first trace top side that is partially covered by the first dielectric layer; a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and a first trace lateral side that is covered by the first dielectric layer; a first conductive via embedded in the first dielectric layer and comprising: a first via top side that is exposed at a top side of the first dielectric layer; a first via bottom side that is directly coupled to the first trace top side; and a first via lateral side that is covered by the first dielectric layer; and a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer; a second redistribution structure on a bottom side of the first redistribution structure and comprising: a second dielectric layer comprising a second dielectric material; a second conductive trace; and a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace; a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure; and a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die.
This semiconductor device features a fine-pitch redistribution structure. A first redistribution layer has a dielectric material with embedded conductive traces and vias. The traces have a top side connected to vias, a bottom side exposed, and lateral sides covered by the dielectric. The vias have a top side exposed, a bottom side connected to the traces, and lateral sides covered. A die interconnection structure sits on top of the vias and extends above the dielectric layer. A second redistribution structure is below the first, with another dielectric layer, conductive traces, and conductive vias connecting the second trace to the first trace. A semiconductor die is attached to the first redistribution structure via conductive bumps on the die interconnection structure. Mold material covers the top of the first redistribution structure and the side of the die.
2. The semiconductor device of claim 1 , comprising an underfill that extends to at least a lateral edge of the first and second redistribution structures.
The semiconductor device described in claim 1 (A semiconductor device comprising: a first redistribution structure comprising: a first dielectric layer comprising a first dielectric material; a first conductive trace embedded in the first dielectric layer and comprising: a first trace top side that is partially covered by the first dielectric layer; a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and a first trace lateral side that is covered by the first dielectric layer; a first conductive via embedded in the first dielectric layer and comprising: a first via top side that is exposed at a top side of the first dielectric layer; a first via bottom side that is directly coupled to the first trace top side; and a first via lateral side that is covered by the first dielectric layer; and a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer; a second redistribution structure on a bottom side of the first redistribution structure and comprising: a second dielectric layer comprising a second dielectric material; a second conductive trace; and a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace; a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure; and a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die) includes an underfill material that extends to at least the lateral edges of both the first and second redistribution structures.
3. The semiconductor device of claim 1 , wherein one of the first and second dielectric materials comprises an inorganic dielectric material, and another of the first and second dielectric materials comprises an organic dielectric material.
The semiconductor device described in claim 1 (A semiconductor device comprising: a first redistribution structure comprising: a first dielectric layer comprising a first dielectric material; a first conductive trace embedded in the first dielectric layer and comprising: a first trace top side that is partially covered by the first dielectric layer; a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and a first trace lateral side that is covered by the first dielectric layer; a first conductive via embedded in the first dielectric layer and comprising: a first via top side that is exposed at a top side of the first dielectric layer; a first via bottom side that is directly coupled to the first trace top side; and a first via lateral side that is covered by the first dielectric layer; and a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer; a second redistribution structure on a bottom side of the first redistribution structure and comprising: a second dielectric layer comprising a second dielectric material; a second conductive trace; and a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace; a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure; and a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die) has different dielectric materials for the first and second redistribution structures. One is an inorganic dielectric, and the other is an organic dielectric.
4. The semiconductor device of claim 1 , wherein the second conductive trace and the second conductive via are portions of a same continuous layer of metal.
In the semiconductor device described in claim 1 (A semiconductor device comprising: a first redistribution structure comprising: a first dielectric layer comprising a first dielectric material; a first conductive trace embedded in the first dielectric layer and comprising: a first trace top side that is partially covered by the first dielectric layer; a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and a first trace lateral side that is covered by the first dielectric layer; a first conductive via embedded in the first dielectric layer and comprising: a first via top side that is exposed at a top side of the first dielectric layer; a first via bottom side that is directly coupled to the first trace top side; and a first via lateral side that is covered by the first dielectric layer; and a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer; a second redistribution structure on a bottom side of the first redistribution structure and comprising: a second dielectric layer comprising a second dielectric material; a second conductive trace; and a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace; a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure; and a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die), the second conductive trace and second conductive via are part of the same continuous metal layer.
5. The semiconductor device of claim 1 , comprising a conductive pillar, wherein: a top side of the conductive pillar, a top side of the mold material, and a top side of the semiconductor die are coplanar; and a bottom side of the conductive pillar is vertically lower than at least a portion of the interconnection structure of the first redistribution structure.
This invention relates to semiconductor packaging, specifically addressing challenges in achieving coplanarity and electrical connectivity in advanced semiconductor devices. The device includes a semiconductor die with an interconnection structure, such as a redistribution layer (RDL), embedded in a mold material. A conductive pillar is formed on the interconnection structure, where the top surfaces of the conductive pillar, the mold material, and the semiconductor die are aligned in a single plane. The bottom of the conductive pillar extends below at least part of the interconnection structure, ensuring robust mechanical and electrical connections. This design facilitates precise alignment and reliable interconnections in stacked or multi-chip configurations, improving manufacturing yield and device performance. The conductive pillar may be formed using electroplating, deposition, or other semiconductor fabrication techniques, and the coplanar arrangement simplifies subsequent processing steps, such as bonding or stacking. The invention is particularly useful in high-density packaging applications where precise alignment and reliable electrical connections are critical.
6. The semiconductor device of claim 5 , wherein the top side of the conductive pillar, the top side of the mold material, and the top side of the semiconductor die are grinded surfaces.
The semiconductor device from claim 5 (The semiconductor device described in claim 1, comprising a conductive pillar, wherein: a top side of the conductive pillar, a top side of the mold material, and a top side of the semiconductor die are coplanar; and a bottom side of the conductive pillar is vertically lower than at least a portion of the interconnection structure of the first redistribution structure) has a specific surface finish. The top surfaces of the conductive pillar, mold material, and semiconductor die are coplanar because they have been grinded to the same level.
7. The semiconductor device of claim 1 , wherein the first conductive trace has no seed layer.
In the semiconductor device described in claim 1 (A semiconductor device comprising: a first redistribution structure comprising: a first dielectric layer comprising a first dielectric material; a first conductive trace embedded in the first dielectric layer and comprising: a first trace top side that is partially covered by the first dielectric layer; a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and a first trace lateral side that is covered by the first dielectric layer; a first conductive via embedded in the first dielectric layer and comprising: a first via top side that is exposed at a top side of the first dielectric layer; a first via bottom side that is directly coupled to the first trace top side; and a first via lateral side that is covered by the first dielectric layer; and a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer; a second redistribution structure on a bottom side of the first redistribution structure and comprising: a second dielectric layer comprising a second dielectric material; a second conductive trace; and a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace; a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure; and a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die), the first conductive trace is manufactured without a seed layer.
8. The semiconductor device of claim 1 , wherein the first conductive trace and other conductive traces of the first redistribution structure have a sub-micron pitch.
In the semiconductor device described in claim 1 (A semiconductor device comprising: a first redistribution structure comprising: a first dielectric layer comprising a first dielectric material; a first conductive trace embedded in the first dielectric layer and comprising: a first trace top side that is partially covered by the first dielectric layer; a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and a first trace lateral side that is covered by the first dielectric layer; a first conductive via embedded in the first dielectric layer and comprising: a first via top side that is exposed at a top side of the first dielectric layer; a first via bottom side that is directly coupled to the first trace top side; and a first via lateral side that is covered by the first dielectric layer; and a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer; a second redistribution structure on a bottom side of the first redistribution structure and comprising: a second dielectric layer comprising a second dielectric material; a second conductive trace; and a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace; a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure; and a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die), the conductive traces in the first redistribution layer are very closely spaced together, exhibiting a sub-micron pitch.
9. A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side.
This semiconductor device includes upper and lower redistribution structures, a semiconductor die, and underfill. The upper redistribution structure consists of a first dielectric layer and a first conductive trace. The lower redistribution structure consists of a second dielectric layer and a second conductive trace electrically connected to the first conductive trace. The semiconductor die is attached to the top of the upper redistribution structure and has a die top side, a die bottom side, and a certain thickness. The underfill extends laterally at least as far as the edge of the upper redistribution structure, with a maximum height at least one-fourth of the die thickness above the die bottom side.
10. The semiconductor device of claim 9 , wherein the maximum height of the underfill is at least as high as the die top side.
In the semiconductor device from claim 9 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side), the maximum height of the underfill reaches at least as high as the top side of the semiconductor die.
11. The semiconductor device of claim 9 , wherein a lateral side of the underfill is coplanar with a lateral side of the upper redistribution structure.
In the semiconductor device from claim 9 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side), the lateral side of the underfill is aligned (coplanar) with the lateral side of the upper redistribution structure.
12. The semiconductor device of claim 9 , wherein the underfill comprises a pre-applied underfill material.
In the semiconductor device from claim 9 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side), the underfill material is pre-applied before die attach.
13. The semiconductor device of claim 9 , comprising an encapsulating material covering at least a portion of the upper side of the upper redistribution structure, wherein the encapsulating material comprises a lateral side that is coplanar with a respective lateral side of the underfill and a respective lateral side of the upper redistribution structure.
The semiconductor device from claim 9 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side) includes an encapsulating material that covers part of the top of the upper redistribution structure. The side of the encapsulating material is aligned (coplanar) with the sides of the underfill and the upper redistribution structure.
14. The semiconductor device of claim 9 , wherein the underfill comprises a capillary underfill material.
In the semiconductor device from claim 9 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side), the underfill material is applied via capillary action.
15. The semiconductor device of claim 9 , comprising: a substrate; conductive interconnection structures connecting a bottom side of the semiconductor die to an upper side of the substrate; and an encapsulating material that covers at least a portion of the upper side of the substrate and laterally surrounds the semiconductor die, the upper and lower redistribution structures, and the conductive interconnection structures, while leaving an upper side of the semiconductor die uncovered by the encapsulating material.
This semiconductor device has a die connected to a substrate using redistribution structures and conductive interconnections. It contains an upper redistribution structure (first dielectric layer and trace) and a lower redistribution structure (second dielectric layer and trace) electrically connected to the first. Conductive interconnection structures connect the bottom of the die to the top of the substrate. An encapsulating material covers the top of the substrate and surrounds the die, redistribution structures, and interconnections, but the top of the die remains exposed. Underfill exists between the die and the upper redistribution structure.
16. The semiconductor device of claim 9 , wherein a portion of the first underfill material is between the semiconductor die and the upper redistribution structure.
In the semiconductor device from claim 9 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a semiconductor die attached to an upper side of the upper redistribution structure, the semiconductor die having die top side, a die bottom side, and a die thickness between the die top side and the die bottom side; and an underfill that extends laterally to at least as far as a lateral edge of the upper redistribution structure, wherein a maximum height of the underfill is at least one fourth of the die thickness above the die bottom side), some of the underfill material is located between the semiconductor die and the upper redistribution structure.
17. A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a first semiconductor die attached to an upper side of the upper redistribution structure; a first underfill between the first semiconductor die and the upper side of the upper redistribution structure and laterally surrounding at least a lower portion of the first semiconductor die; a second semiconductor die attached to the upper side of the upper redistribution structure; a first mold material covering at least a portion of the upper side of the upper redistribution structure and at least a portion of a lateral side of the first semiconductor die; and a second mold material, distinct from the first mold material, that laterally surrounds at least the second semiconductor die.
This semiconductor device features upper and lower redistribution structures, two semiconductor dies, and two different mold materials. The upper redistribution structure includes a first dielectric layer and a first conductive trace. The lower redistribution structure has a second dielectric layer and a second conductive trace connected to the first. A first semiconductor die is attached to the top of the upper redistribution structure, with a first underfill between them that also surrounds the bottom of the die. A second semiconductor die is also attached to the upper redistribution structure. A first mold material covers the top of the redistribution structure and part of the side of the first die. A second, distinct mold material surrounds at least the second die.
18. The semiconductor device of claim 17 , wherein the second mold material extends laterally outward in all lateral directions farther than the first mold material.
In the semiconductor device from claim 17 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a first semiconductor die attached to an upper side of the upper redistribution structure; a first underfill between the first semiconductor die and the upper side of the upper redistribution structure and laterally surrounding at least a lower portion of the first semiconductor die; a second semiconductor die attached to the upper side of the upper redistribution structure; a first mold material covering at least a portion of the upper side of the upper redistribution structure and at least a portion of a lateral side of the first semiconductor die; and a second mold material, distinct from the first mold material, that laterally surrounds at least the second semiconductor die), the second mold material extends further outward in all directions than the first mold material.
19. The semiconductor device of claim 18 , wherein the second mold material laterally surrounds the first mold material.
In the semiconductor device from claim 17 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a first semiconductor die attached to an upper side of the upper redistribution structure; a first underfill between the first semiconductor die and the upper side of the upper redistribution structure and laterally surrounding at least a lower portion of the first semiconductor die; a second semiconductor die attached to the upper side of the upper redistribution structure; a first mold material covering at least a portion of the upper side of the upper redistribution structure and at least a portion of a lateral side of the first semiconductor die; and a second mold material, distinct from the first mold material, that laterally surrounds at least the second semiconductor die) and claim 18 (the second mold material extends laterally outward in all lateral directions farther than the first mold material), the second mold material also laterally surrounds the first mold material.
20. The semiconductor device of claim 17 , wherein the second semiconductor die is attached to the upper side of the upper redistribution structure such that the second semiconductor die is electrically coupled to the first semiconductor die.
In the semiconductor device from claim 17 (A semiconductor device comprising: an upper redistribution structure comprising: a first dielectric layer comprising a first dielectric material; and a first conductive trace; a lower redistribution structure comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a first semiconductor die attached to an upper side of the upper redistribution structure; a first underfill between the first semiconductor die and the upper side of the upper redistribution structure and laterally surrounding at least a lower portion of the first semiconductor die; a second semiconductor die attached to the upper side of the upper redistribution structure; a first mold material covering at least a portion of the upper side of the upper redistribution structure and at least a portion of a lateral side of the first semiconductor die; and a second mold material, distinct from the first mold material, that laterally surrounds at least the second semiconductor die), the second semiconductor die is attached to the upper redistribution structure so that it is electrically connected to the first semiconductor die.
(0-5s) HOOK: [Upbeat, futuristic music starts. Quick montage of sleek, ultra-thin devices: smartphone, smartwatch, drone.] Ever wonder how your favorite gadgets keep getting impossibly thin, yet incredibly powerful? The secret lies deep inside, at the microchip level!
(5-20s) PROBLEM: [Visual: Zoom into a schematic of a traditional, slightly bulky microchip package. Show 'thick' connections.] For years, engineers faced a huge challenge: how to cram more and more connections into a tiny microchip without making the whole thing bigger or slower. Traditional packaging methods often meant compromises – either thicker devices or less reliable connections for those crucial, fine-pitch wires.
(20-50s) SOLUTION: [Visual: Transition to a modern, sleek animation of the 'Semiconductor Package and Fabricating Method Thereof' concept. Show ultra-thin, layered connections forming with precision.] But now, a groundbreaking innovation, the Semiconductor Package and Fabricating Method Thereof patent, is changing everything! This technology introduces a revolutionary way to build semiconductor packages with ultra-thin, fine-pitch redistribution structures. Imagine building microscopic, multi-layered highways for data, perfectly stacked and incredibly dense. This innovation allows for more intricate circuitry in a smaller footprint, boosting performance, reducing size, and making our devices faster and more efficient than ever before!
(50-60s) CALL-TO-ACTION: [Visual: Patentable.app logo appears with the patent number and title. Text overlay: 'Learn More: patentable.app/patents/US-9852976'] This isn't just a technical marvel; it's the future of electronics. Want to dive deeper into how the Semiconductor Package and Fabricating Method Thereof is powering the next generation of tech? Visit patentable.app/patents/US-9852976 to explore the full details!
HOOK 1 (0-3s): 🤯 Is your phone getting magically thinner and faster? HOOK 2 (0-3s): Ever wonder how microchips keep shrinking but get more powerful? HOOK 3 (0-3s): What if I told you a patent could make your next device ridiculously small AND super fast?
PROBLEM (3-15s): Traditional microchip packaging hits a wall. We need more connections in less space, but making those tiny wires (fine-pitch redistribution layers) without errors is incredibly tough. Chips get thicker, slower, or harder to make.
SOLUTION (15-45s): Enter the Semiconductor Package and Fabricating Method Thereof patent! This groundbreaking innovation introduces a new way to build semiconductor packages with ultra-thin, super-dense wiring. Imagine building a tiny, multi-story highway system inside your chip, making it incredibly efficient and compact. This technology solves the 'space crunch' by precisely layering connections, leading to thinner devices, better performance, and easier manufacturing.
CTA (45-60s): Want to dive deeper into this microchip revolution? Learn how the Semiconductor Package and Fabricating Method Thereof is shaping the future of tech. Hit the link in bio or visit patentable.app to explore the full patent details! #Semiconductor #Innovation #Microchips #AdvancedPackaging #TechExplained #FutureIsNow
HOOK 1 (0-5s): What if the secret to your next super-fast, ultra-thin device is already patented? HOOK 2 (0-5s): Ever wondered how our devices keep getting smaller and more powerful? The answer lies in advanced packaging, and a new patent is leading the charge!
INTRO (0-5s): Today, we're uncovering the brilliance behind the patent titled Semiconductor Package and Fabricating Method Thereof – a true game-changer in the world of microchips.
CONTEXT (5-20s): For decades, the electronics industry has battled a critical challenge: how to pack more processing power into smaller spaces. As chips become more complex, the connections within them (redistribution layers) must become incredibly fine and thin, a task that's notoriously difficult and prone to errors with traditional methods.
INNOVATION (20-60s): This is where the Semiconductor Package and Fabricating Method Thereof steps in. This invention introduces a revolutionary approach to creating semiconductor packages with ultra-thin, fine-pitch redistribution structures. Imagine building a skyscraper of incredibly precise, microscopic wires. This innovation uses advanced fabrication techniques to ensure these layers are not only thin but also highly reliable and efficient. It means designers can create more intricate chip layouts without increasing the overall package size, leading to significant boosts in performance and massive reductions in thickness.
IMPACT (60-80s): The implications are huge! From enabling the next generation of AI-powered devices and ultra-compact wearables to enhancing high-performance computing, this technology provides the foundational packaging necessary for continued innovation. It's about more than just speed; it's about enabling entirely new product categories and capabilities.
CLOSING (80-90s): The Semiconductor Package and Fabricating Method Thereof isn't just a technical marvel; it's a commercial catalyst. Want to dive into the full details and understand its market potential? Find the link in our description or visit patentable.app/patents/US-9852976. Don't miss out on understanding the future of tech!
VISUAL HOOK (0-2s): [Fast-paced visual of a spinning microchip transforming into a super-thin smartphone.]
PROBLEM (2-15s): Ever wonder why your devices keep getting thinner, yet more powerful? It’s a huge challenge to cram more tech into less space. We need super-tiny, super-precise connections inside chips, and old methods just can't keep up!
SOLUTION (15-35s): This is where the Semiconductor Package and Fabricating Method Thereof patent changes EVERYTHING! 🤯 It introduces an incredible way to build semiconductor packages with ultra-thin, fine-pitch redistribution structures. Think microscopic, perfectly laid-out highways for data inside your chip! This innovation means smaller, faster, and more reliable devices are now possible, opening doors for the next wave of smart tech.
CTA (35-45s): Mind blown? 🤯 Get the full scoop on how the Semiconductor Package and Fabricating Method Thereof is powering the future! Link in bio for all the details! #Semiconductor #TechInnovation #Microchip #AdvancedPackaging #Engineering #Patent #FutureDevices
Hero image showing a detailed cross-section of an advanced semiconductor package, illustrating the thin, fine-pitch redistribution layers (RDLs) enabled by the Semiconductor Package and Fabricating Method Thereof patent.
Technical flowchart illustrating the multi-step fabrication process for creating fine-pitch redistribution structures as described in the Semiconductor Package and Fabricating Method Thereof patent.
Abstract illustration symbolizing the enhanced miniaturization, efficiency, and high-density connectivity achieved by the Semiconductor Package and Fabricating Method Thereof.
Infographic comparing prior art semiconductor packaging with the advanced, thin, fine-pitch structures enabled by the Semiconductor Package and Fabricating Method Thereof, highlighting benefits in thickness, pitch, and performance.
Social media card announcing the Semiconductor Package and Fabricating Method Thereof patent, highlighting its benefits for microchip technology and miniaturization.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 6, 2017
December 26, 2017
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