Dynamic measurement of frequency synthesizer noise spurs or phase noise

Notice: more than one reissue application has been filed for the reissue of U.S. Pat. No. 9,696,359, The reissue applications are: U.S. patent application Ser. No. 16/503,240, filed Jul. 3, 2019, now Reissue Pat. No. RE48613, U.S. patent application Ser. No. l7/l54,6l1, filed Jan. 21, 2021, where U.S. patent application Ser. No. 17/154,611 is a continuation reissue of U.S. patent application Ser. No. 16/503,240, and U.S. patent application Ser. No. 18/143,211, filed May 4, 2023, is a continuation reissue of U.S. patent application Ser. No. 17/154,611. This application is a continuation reissue of U.S. patent application Ser. No. 17/154,611, which is a continuation reissue of U.S. patent application No. 16/503,240, which is a reissue of U.S. Pat. No. 9,696,359, filed on Dec. 31, 2014, and issued Jul. 4, 2014. The above referenced applications are hereby incorporated by reference.

Disclosed embodiments relate to dynamic measuring noise spurs or the phase noise generated by frequency synthesizers.

A frequency synthesizer comprises an electronic system which generates at its output a higher frequency signal(s) from the lower frequency signal received from a single fixed time base or master oscillator. A common way to implement a frequency synthesizer is with a phase-locked loop (PLL).

A PLL is a feedback control system that includes an error detector (comprising a phase frequency detector coupled to a charge pump) which compares the phases of two input signals (reference frequency signal and frequency divided higher frequency output signal) to produce an error signal that is proportional to the difference between their phases. The error signal is then low pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates the higher output frequency. The output frequency is fed back through a frequency divider to the input of the phase frequency detector, producing a negative feedback loop. If the output frequency drifts, the phase error signal will increase, driving the frequency in the opposite direction so as to reduce the frequency error. Thus, the output is locked to the frequency at the other (reference) input of the error detector. This reference input is usually derived from a crystal oscillator, which is stable in frequency.

One application for frequency synthesizers is for enabling flexible and cost-effective implementation of frequency modulated continuous wave (FMCW) radar systems. For example, automotive radar systems use frequency synthesizers to generate a continuous wave (CW) of constant frequency or time-varying frequency. Since the driver's safety is critical in automotive applications, it is important to continually monitor the performance of the frequency synthesizer with respect to the phase noise in the frequency synthesizer output continuously. Higher phase noise during on field operation relative to a certain acceptable noise level expected during the design of the radar apparatus can cause the radar apparatus to potentially fail to detect some surrounding obstacles. False detection of obstacles where there is actually none is also likely in the presence of phase spurs in the synthesizer output. Hence high phase noise or spurs may render the radar measurements unreliable.

This Summary briefly indicates the nature and substance of this Disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Disclosed embodiments provides phase noise (PN) measurement circuitry and related methods that can dynamically estimate the PN across a band of frequencies or phase spurs at particular spurious frequency(ies) (spurs) undesirably generated by a phase-locked loop (PLL)-based frequency synthesizer which includes an error detector at its input. As known in the art, spurs are at specific frequencies that usually appear as small amplitude spikes near the carrier frequency, as opposed to PN which is viewed over a range (or band) of frequencies and includes broadband noise generated by all electronic components, and includes shot noise and thermal noise, as well as the noise spurs.

The PN measurement circuitry generally includes its own “replica” PN measurement error detector that receives the same reference frequency signal and divided frequency signal received by the error detector of the frequency synthesizer. The output from the PN measurement error detector is current-to-voltage converted, amplified, digitized, then frequency analyzed to generate a PN measurement at one or more frequencies including a spur (at one or more discrete frequencies) or a PN measure. The term “PN measurement” when referring to spurs is a collection of information which may include whether there exists a spur at one or more frequencies of interest, the spur's magnitude (in dB or dBc) if it exists, and the PN measure referring to the frequency synthesizer's PN power spectral density in some band in the vicinity of that frequency (expressed in dB/Hz or dBc/Hz).

By utilizing a disclosed replica PN measurement error detector, disclosed embodiments essentially avoid perturbing the frequency synthesizer. In a typical implementation the PLL error detector comprises a phase frequency detector (PFD) followed by a charge pump (CP), where the output of the CP is a current which is used by the PN monitor to monitor the operation of the frequency synthesizer. Hence, in this embodiment a replica error detector is used including both a replica PFD and a replica CP. However, in another embodiment, the same PFD as the frequency synthesizer is also used (shared) by the PN measurement circuitry so that the PN measurement circuitry has only a replica CP.

The replica PN error detector or replica CP is configured to match the error detector or CP of the frequency synthesizer. In one embodiment the frequency synthesizer and PN measurement circuitry are both formed in and on the same semiconductor substrate “chip” to provide built-in-self-testing (BIST) for the frequency synthesizer.

As used herein, the replica PN error detector or replica CP is a scaled copy of the components of the error detector (e.g., D-type flip flops of the PFD and positive and negative current sources of the CP of the frequency synthesizer). The replica PN error detector or replica CP is generally fabricated on the same semiconductor substrate as the PLL-based frequency synthesizer, in some embodiments. In some of these embodiments the replica PN error detector or replica CP is also fabricated in close proximity (defined herein as the respective blocks being within 200 μm of one another to the error detector or CP of the frequency synthesizer), such as on a common CMOS die.

Placing the replica PN error detector or replica CP close to the error detector or CP of the frequency synthesizer enables both good transistor matching and a good fit of the error detector response including the noise performance from the replica error detector or replica CP to the response from the error detector or CP of the frequency synthesizer. The scale of the replica PN error detector or replica CP can be larger than the size of the error detector or CP of the frequency synthesizer in some embodiments so that its contribution to overall PN or spurs is lower, though the scale is not necessarily limited to being larger and can be essentially the same size defined herein as being within 20% of one another. In one example embodiment, the respective replica components are about 1.2 times to 5 times the size of the corresponding components in the error detector of the frequency synthesizer.

Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

Disclosed embodiments provide PN measurement circuitry and related methods for measuring the PN of a PLL-based frequency synthesizer, where the PN measurement circuitry includes at least a replica CP, and in some embodiment includes a replica PN measurement error detector including both a replica PFD and a replica CP. The PN measurement circuitry also includes circuitry for amplifying the phase error output provided by the replica PN measurement error detector, as well as circuitry for digitizing, and performing a Fourier transform (FT, e.g., FFT) to measure frequency PN or spur(s) (e.g., 1 MHz PN/spurs). As described above, disclosed PN measurement circuitry can be on the same semiconductor substrate chip as the frequency synthesizer to provide BIST.

is a flow chart that shows steps in an example methodof dynamic measurement of frequency synthesizer noise spurs or PN, according to an example embodiment. Stepcomprises providing (i) a PLL-based frequency synthesizer that includes a first error detector including a first PFD having an input receiving a reference frequency signal coupled to a first CP that is coupled to a voltage controlled oscillator (VCO) having an output fed back to the error detector through a feedback divider that provides a divided frequency signal to another input of the first PFD, where the first PFD outputs an error signal and (ii) PN measurement circuitry comprising at least a replica CP coupled to an output of a second PFD or coupled to an output of the first PFD.

Stepcomprises receiving the error signal at an input of the replica CP or the divided frequency signal and reference frequency signal at an input of a second PFD, wherein an output of the replica CP provides a scaled phase error current. In one embodiment the PN measurement circuitry includes the second PFD to provide a replica PN measurement error detector (see the replica PN error detectorof PN measurement circuitryshown indescribed below), so that the first PFD and second PFD are separate PFDs. In another embodiment the PN measurement circuitry shares the first PFD with the frequency synthesizer.

Stepcomprises current-to-voltage converting and amplifying the scaled phase error current to provide an amplified phase error voltage. A transimpedance amplifier can be used for providing both the current-to-voltage converting and signal amplifying. Stepcomprises digitizing the amplified phase error voltage to provide a digital phase error signal, such as using an analog-to-digital converter (ADC). However, besides stepcomprising current-to-voltage converting then stepcomprising digitizing a voltage signal, it may be possible to use other techniques to generate a digital phase error signal from the scaled phase error current.

Stepcomprises frequency analyzing the digital phase error signal to generate a PN measurement at one or more frequencies, such spur(s) around the carrier frequency or a PN spectrum (e.g., spanning at least 4 decades of frequency). For example, the digitized signal's spectrum can be measured using a microcontroller unit (MCU), digital signal processor (DSP) unit or a FFT unit. Stepcomprises comparing the PN measurement (e.g., power spectral density (PSD)) to a threshold PN measure to determine whether the PLL frequency synthesizer is operating within a specified PN limit. Based on design knowledge (e.g., simulation across voltage and temperature) of the approximate PLL bandwidth, input phase to output phase response and VCO phase to output phase response, a threshold PN measure can be determined.

Any uncertainty in the knowledge of these parameters may be accommodated as an inaccuracy in the synthesizer output noise measurement, where the prediction of synthesizer output noise power or PSD from the measured spectrum is referred to as the synthesizer output noise measurement. It is generally useful to inform the radar system's central processor unit (CPU) or other processor that the frequency synthesizer has degraded in performance with respect to designed expectations, when the measured PN (e.g., PSD) is poorer as compared to programmed noise thresholds. In that case the frequency synthesizer can be automatically disabled as automotive systems are “safety-critical”, so that the user can return to manual operation, such as driving without driver assist for automotive applications.

In one particular embodiment the frequency synthesizer provides an 80 GHz output and the PN measurement circuitry detects and reports any degradation in the synthesizer's PN noise performance within 50 ms, such as reporting the degradation to an associated radar system CPU. In another embodiment, the PN measurement(s) are themselves reported to the radar's CPU or other processor, and the radar system's parameters are modified based on this measurement. For example, if the PN measurement indicates higher PN, radar detection algorithms implemented by the CPU may analyze the radar received signal for longer durations before confirming detection of obstacles.

is a block diagram representation of an example circuit combinationcomprising a frequency synthesizerand PN measurement circuitrycoupled to receive the same reference frequency signal and divided frequency signal received by the error detector of the frequency synthesizer, all on a common semiconductor substrate, according to an example embodiment. The operating frequencies shown ininclude a 900 MHz carrier frequency and 20 GHz voltage controlled oscillator (VCO)which are only provided as an example to help clarify operation of the circuit combinations shown.

The PLL frequency synthesizerincludes an error detectorcomprising a PFDa and CPb coupled to receive the 900 MHz reference frequency signal having an output coupled to a low pass filter (LPF)then to VCOshown providing a 20 GHz output having an output fed back to the error detectorafter frequency division by a feedback dividerto provide a divided frequency signal. An optional times 4 (×4) frequency multiplieris shown coupled to an output of the VCOto provide the 80 GHz output shown. The configurations shown are only examples and different combinations of synthesizer (or VCO) frequency and frequency multiplier are possible. However, for ease of explaining the rest of the circuits, certain numbers are used in the rest of this description.

The PN measurement circuitryincludes a replica PN measurement error detectorshown as PFD/CP including PFDa and CPb that is coupled to receive the divided frequency signal and the 900 MHz reference frequency signal at respective inputs, and for outputting a scaled phase error current having the phase error shown scaled by 900 MHz/80 GHz. A current-to-voltage (I to V) converteris for current-to-voltage converting and an amplifieris for amplifying the scaled phase error current to provide an amplified phase error voltage. An analog-to-digital converter (ADC)is for digitizing the amplified phase error voltage to provide a digital phase error signal. A LPFis shown between the amplifierand ADC.

A processor(CPU, DSP, or MCU) that includes an associated memoryprovides frequency analyzing shown as including an FFT blocka which processes the digital phase error signal and generates a PN measurement that is coupled to a threshold comparing blockb provided by the processorfor comparing the measured PN at one or more frequencies (spurs) or a PN spectrum to a threshold PN measure to determine whether the frequency synthesizeris operating within a specified noise limit. In operation of circuit combination, the processorof the PN measurement circuitrytranslates the noise signal at the output of the ADCto PN by knowing the CP current of the replica PN measurement error detector, and the gain of the current to voltage converterand amplifier. For the example operating frequencies shown, the PN measured at the output of the replica PN measurement error detectoris the root mean squared (rms) addition of PN at 1 MHz offset from the 900 MHz reference noise+1 MHz offset VCONoise.

The LPFtypically having about a 500 kHz bandwidth filters the 1 MHz reference noise by about 6 dB, but does not filter the 1 MHz VCO noise. Due to this difference, the measurement of sum total PN may be inaccurate by 0 to 6 dB vs. the actual PN generated by the frequency synthesizer. However, the amount of attenuation of VCO noise and reference noise at any frequency is generally predictable from design knowledge and/or the knowledge of the PLL loop bandwidth (which is measurable through calibration procedures known to one skilled in the art). Based on which of the noise sources dominates at any frequency (typically known during the design of the PLL or manufacturing or testing of the chip), appropriate correction scale factors (multiplicative in normal number units and additive in dB units) can be applied during the processing of the digital samples output by the PN measurement circuitry's ADC.

In the event that both the VCO and reference noise contribute significantly and similarly to the synthesizer output noise, in one embodiment, the above inaccuracy and the inaccuracy due to other noises and mismatches may be handled by using appropriately modified (typically relaxed) PN comparison thresholds used in determining the occurrence of frequency synthesizer failure. In most safety critical automotive radar applications, such relaxation may be acceptable. In typical frequency synthesizers, the relaxation may be lower than only 6 dB, which means that indication to the radar's CPU may be possibly given by processing the PN measurement circuitry and associated digital processing, if and when the synthesizer PN performance degrades by higher than 6 dB than specification levels. In one embodiment, such inaccuracy may be handled by using stricter PN comparison threshold, so that the frequency synthesizer is deemed to be meeting its PN performance requirements only if the measured PN is 6 dB lower than acceptable levels. In such a case, the reporting of frequency synthesizer failure is pessimistic.

In a typical example frequency synthesizer considered in the Examples section described below, after accounting as described above and for other noises and mismatches it is predicted a ±4 dB accuracy is provided in the −102 dBc/Hz 80 GHz PN level estimation. The ±4 dB accuracy easily satisfies typical safety compliance goals and is a major advance from known techniques that are not able to measure the PN of a frequency synthesizer. PN measurement circuitrycan also detect −45 dBc to −60 dBc spurs at 80 GHz depending on allowed on-field test time (e.g., 100 μs to 5 ms).

In one arrangement on the same semiconductor substrate there is also formed a radar receiver (RX).is a block diagram representation of an example circuit combinationcomprising a frequency synthesizerand PN measurement circuitry′ including a replica PN measurement error detectorcoupled to receive the same reference frequency signal and divided frequency signal received by the error detector of the frequency synthesizer configured for providing dynamic measurement of the noise spurs or PN generated by the frequency synthesizer, all on a common semiconductor substratetogether with RX, according to an example embodiment. In this embodiment the PN measurement circuitryand RXcan share several circuit blocks including at least the ADCand processor shown as a CPU′ (as well as the amplifierand LPFas shown), to conserve die area and reduce cost.

As shown in, the RXand PN measurement circuitrythus share the amplifier, LPF, ADC, CPU′ and memory. As a result, circuit combinationmay only occupy about <<0.05 mmof chip area due to sharing of circuit blocks including the generally relatively large area ADCwith the RX. Time multiplexing can be used to share amplifierand ADCbetween RXand PN measurement circuitry. For applications such as frequency modulated continuous wave (FMCW) radar, during the inter-frame intervals when the RXis not receiving any signal, so that the amplifierand ADCcan be used by the PN measurement circuity, while in normal operation when the RXis demodulating the received FMCW signals amplifierand ADCcan be used by the RX. Inter-frame time refers to the time when the FMCW radar chip is not chirping or transmitting chirps and processing the received signal for performing detection of objects around the FMCW radar apparatus and computing their location and velocity.

is a block diagram representation of an example circuit combinationcomprising a frequency synthesizerand PN measurement circuitry″ that shares the same (common) PFDa as the frequency synthesizer and includes a replica CPb coupled to receive the error signal generated by the PFDa configured for providing dynamic measurement of the noise spurs or PN generated by the frequency synthesizer, all on a common semiconductor substrate, according to an example embodiment. This embodiment has the advantage of a further reduced die area compared to circuit combinationshown in.

is a circuit and block diagram representation of an example single chip combination circuitthat includes PN measurement circuitry′″ providing BIST for providing PN measurements for the PN generated by the PLL frequency synthesizer′, according to an example embodiment. There is a buffershown connected between the output of the LPFat the node shown as VCNT (that is an arbitrary voltage) which provides its input and the node that provides inputs to both I2Vand an input of the amplifierat its output. Because the output of the bufferis fed to the input of the I2Vand to an input of the amplifier, the noise in the bufferand the arbitrary reference voltage VCNT gets cancelled. The VCO block of the frequency synthesizer′ is shown as′ and includes a VCOand a buffera. The divider of the frequency synthesizer′ is shown as′ and includes a ramp generatora, a digital high speed ΣΔ (sigma delta) modulatorb and a % N″ circuitc.

The ramp generatora is generally digital hardware that can generate triangular, saw-tooth or staircase waveforms in order for the frequency synthesizer′ to output a CW whose frequency varies over time in a triangular, saw-tooth, stair-step fashion, respectively. The ramp generatora can also generate a constant output so that the frequency synthesizer's output is a CW of constant frequency. The ramp generator's digital output is given to a digital high speed signal delta modulatorb that is operating on the divider's output clock and provides to the % N circuitc at every output clock of the divider, a division factor that it should divide the divider's input clock by, during the subsequent output clock cycle. The % N circuitc is generally a digital state machine that creates an output clock whose cycle length (or period) is the division factor N times the divider's input clock period. The division factors are generally positive integers (e.g., 19, 20, 21) and ramp generator's digital output is a digital word with a very fine resolution, (e.g., 0.001, so that it can represent values such as 18.998, 18.999, 19, 19.001, . . . , 19.501, 19.502, . . . , 20, 20.001, . . . 21, 21.001, 21.002, . . . The digital high speed sigma delta modulatorb operates in a way such that the local average of its integer output is equal to that of the ramp generator's digital output.

The processing of the ADC output samples to find synthesizer PN and spurs can be performed in hardware and/or in processor such as in software or firmware. Such processing is explained in two example embodiments below.

The processing is explained for the first embodiment using equations or processing steps described below:

The signal processing is explained in another embodiment using equations or processing steps described below. This processing can be performed in hardware coupled to the ADC or in the form of software or firmware in the processor and in the following explanation, the digital hardware based processing method is explained.

In one embodiment a radar apparatus comprises the synthesizer and PN measurement circuitry, transmitter circuits, receiver circuits, ADC and digital processors to detect the presence, location and velocity of surrounding objects. The synthesizer is employed to generate a CW signal of constant frequency or stepped frequency (staircase, where at each frequency, a certain duration of time is spent) or triangular frequency (where frequency increases for a certain time duration and then decreases for a certain time duration) or saw-tooth frequency (where frequency increases/decreases for a certain duration and then returns to the starting frequency quickly) for a certain duration of time, during which the radar apparatus's transmitter is made to emit the signal and receiver's output is processed to detect presence, location and velocity of surrounding objects (collectively called radar processing).

Such a process is repeated after a certain time gap. During this time gap, when the synthesizer is not engaged in the radar processing, the synthesizer is made to generate a CW signal of a similar frequency pattern as during radar processing and the PN measurement circuitry and associated computations are employed to measure the synthesizer PN and determine if it is within acceptable limits. Hence, the PN measurement process may be performed at regular intervals when the synthesizer is not engaged in radar processing, such as every 100 ms, the PN measurement process being repeated.

A synthesizer that generates a staircase, triangular or saw-tooth frequency is said to be an FMCW synthesizer and the signal generated is said to be an FMCW signal. The ramp generatora is generally digital hardware that can generate triangular, saw-tooth or staircase waveforms in order for the frequency synthesizer′ to output a CW whose frequency varies over time in a triangular, saw-tooth, staircase fashion respectively. It can also generate a constant output so that the frequency synthesizer output is a CW of constant frequency.

In another embodiment the PN measurement circuitry reuses some parts/circuits of the radar apparatus's receiver, such as the amplifiers and ADC that are engaged in the radar processing are used for PN measurement process, when the PN measurement is performed in time slots when the normal radar processing is not ongoing. In another embodiment, the PN measurement circuitry does not reuse any parts/circuits of the radar apparatus's receiver. In that embodiment, the PN measurement process is performed during the radar processing itself.

is a block diagram depiction of an example radar apparatusconfigured so that the PN measurement circuitry digital process blockis independent of normal radar receiver path, according to an example embodiment. Radar apparatusis shown including in series connection mm-wave or RF amplifier, mixer, amplifier, LPF, ADCand radar signal processor′. Radar apparatusalso includes a transmitter circuit.

An output of the frequency synthesizer′ is coupled to an input of the transmitter circuitand the mixer. Another output of the frequency synthesizer′ is coupled to an input of a synthesizer PN measurement circuitry and digital process block. The frequency synthesizer′ is an FMCW synthesizer and its output signal is amplified and transmitted on air by the transmitter circuit. Reflections of that transmitted signal from objects near the radar apparatus are received and amplified by mm-wave or RF amplifierand the amplified output is mixed with the FMCW synthesizer output by mixerand the mixer's output is amplified by amplifier, low pass filtered by LPF, digitized by ADCand digitally processed by the radar digital processor′.

is a block diagram depiction of an example radar apparatusconfigured so the PN measurement circuitry digital process blockreuses/shares circuits of the normal radar receiver path of the radar apparatus, according to an example embodiment. Only one of the paths is engaged/active at any given time, with the other path being disabled. In this embodiment the output of the ADCis coupled to an input of the synthesizer PN measurement circuitry and digital process block.

The frequency synthesizer′ is an FMCW synthesizer and its output signal is amplified and transmitted on air by the transmitter circuit. Reflections of that transmitted signal from objects near the radar apparatus are received and amplified by mm-wave or RF amplifierand the amplified output is mixed with the FMCW synthesizer output by mixerand the mixer's output is amplified by amplifier, low pass filtered by LPF, digitized by ADCand digitally processed by the radar digital processor′. In order to reduce the semiconductor (e.g., silicon) chip area additionally needed for the PN measurement circuitry, the radar receiver's amplifier, LPFand ADCare reused for the PN measurement, so that no such extra circuits are needed to be placed on the chip explicitly and dedicated only for the PN measurement.

In the disclosed radar apparatuses, there are durations when normal radar operation is halted and such halt periods occur between durations where normal radar operation occurs. In a circuit combination as shown in, when normal radar operation is not occurring, the PN measurement process is performed and the ADC's output is used by the digital processor of the PN measurement circuitry digital process block. At the same time it is made sure that the mixer's output doesn't cause changes to the amplifier's input and only the current to voltage convertor's output drives the amplifier. When normal radar operation is occurring, the PN measurement process is not performed simultaneously and the ADC's output is not used by the digital processor of the PN measurement circuitry digital process block. At that time it is made sure that only the mixer's output drives the amplifier's input and the current to voltage convertor's output does not cause changes to the amplifier's input. One way of ensuring that a circuit (e.g. mixeror current to voltage converter) doesn't cause change to amplifier's input is by powering down that circuit, while the other circuit is operational. Many other similar circuit methods exist for achieving the same result that will be apparent to those having ordinary skill in the art.

A radar apparatus disclosed herein uses a FMCW synthesizer and PN measurement circuitry and method. The radar apparatus performs normal radar processing (transmitting an FMCW signal and receiving reflections from obstacles and processing the received signal to detect presence, position and velocities of the obstacles) and PN measurement process. The radar apparatus, in at least some embodiments, also includes a PN measurement scheduler, which is a digital finite state machine. The digital finite state machine can be implemented using software or firmware or hardware and controls when the PN measurements and when the normal radar processing are conducted.,anddescribed in the Examples below illustrate some ways the PN measurement scheduler causes normal radar processing and PN measurement to occur.

Advantages of disclosed embodiments include on-chip dynamic PN measures for a frequency synthesizer, such as in one embodiment to provide a prompt message to radar controller unit if the synthesizer fails in meeting its expected performance levels during field usage, and the PN measurement can be carried out on the frequency synthesizer in the same (FMCW) mode as it is used in during normal radar operation. Products that may utilize disclosed embodiments include the Texas Instrument Incorporated's AR12xx, AR16xx or automotive radar product line which are radar sensors for advanced driver assistance, collision avoidance, parking assist, and automated braking.

Disclosed embodiments are further illustrated by the following specific Examples, which should not be construed as limiting the scope or content of this Disclosure in any way.

provides a data table which shows calculated measured parameters obtained from the combination circuitshown inincluding PN as a function of the offset frequency from a 900 MHz carrier frequency. I=1.256 mA (where Icp2 is the replica PFD/CP current of the replica PN measurement error detector), Rin LPF=10 kΩ and V(input referred voltage noise of the I2V converter)=5 nV/√Hz. The PN measured can be seen to be at a higher level as compared to the ADC noise, so that the PN can be measured by the PN measurement circuitry′″ including ADC. The ADC noise PSD is at −146 dBV rms/Hz.

As shown inthe noise PSD created by PN monitor circuitry′″ at the input to the ADCdue to PN at various offsets is greater than the ADC noise PSD. For example, the PN at 1 MHz offset translates to −118 dBV rms/Hz whereas the ADC noise PSD itself is −146 dBV rms/Hz.