Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

This application is areissue application for U.S. Pat. No. 10,684,793 issued on Jun. 16, 2020 on U.S. application Ser. No. 15/462,347 filed on Mar. 17, 2017, which is aContinuation of U.S. application Ser. No. 14/992,472, filedonJan. 11, 2016, (now U.S. Pat. No. 9,632,856, issued Apr. 25, 2017), which is a Divisional of U.S. application Ser. No. 13/910,591, filed Jun. 5, 2013, (now U.S. Pat. No. 9,268,636, issued Feb. 23, 2016), which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2013-0020674, filed on Feb. 26, 2013, in the Korean Intellectual Property Office, the entire contents of each of which are incorporated herein by reference.

Field

Example embodiments relate to semiconductor memory devices and methods of operating the same, for example, semiconductor memory devices including error correction circuits and methods of operating semiconductor memory devices.

Description of Conventional Art

Capacity and speed are increasing for semiconductor memory devices that are widely used in high performance electronic systems. A dynamic random access memory (DRAM), which is an example of a semiconductor memory device, is a memory that determines data by using charges stored in a capacitor.

While process scaling continues, a bit error rate (BER) of semiconductor memory devices may increase. Thus, resources such as repair cells may have to be increased to provide data reliability in response to the increase in the BER. However, if the resources increase, chip size overhead may increase, and ensuring stable operation of the semiconductor memory device at a relatively high BER may be more difficult.

Example embodiments provide semiconductor memory devices in which errors that may occur when data is accessed may be more stably corrected and/or an error correction speed may be improved, and methods of operating semiconductor memory devices. Example embodiments also provide memory systems, memory controllers, memory modules, computer systems, and methods of operating the same.

According at least some example embodiments, data errors may be more stably corrected even when bit error rates (BERs) increase, and an increase in required resources relative to the increase of the BER may be reduced.

In addition, multi-bit errors may be corrected, and thus, reliability of data may be improved. An increase in overhead generated in terms of timing by correction of the multi-bit error may be reduced and/or minimized, thereby improving performance of the semiconductor memory device.

At least one example embodiment provides a memory controller including: a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data.

At least one other example embodiment provides a memory device comprising: an error correction circuit configured to correct errors in data read from a memory cell in response to a first command; and a data output circuit configured to output the corrected data in response to a second command.

At least one other example embodiment provides a memory device including: an error detector configured to detect a number of error bits in data read from a memory cell in response to a first command; a data storage circuit configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value; and an error correction circuit configured to correct the stored data.

At least one other example embodiment provides a memory device including: an error detector configured to detect a number of error bits in data read from a memory cell in response to a received first command; and a correction status information generator configured to output correction status information associated with the read data, the correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value.

At least one other example embodiment provides a memory device including: an error detector configured to detect a number of error bits in data read from a memory cell in response to a first command; a data storage circuit configured to store the read data in a data storage circuit if the detected number of error bits is greater than or equal to a first threshold value; a management circuit configured to check a data storage status indicator in response to a second command, the data storage status indicator indicating whether the read data is stored in the data storage circuit; and a data output circuit configured to output one of corrected data from the data storage circuit and second data from the memory cell based on the data storage status indicator.

At least one other example embodiment provides a memory device including: an error detector configured to detect a number of error bits in data read from a memory cell in response to a first command; a data storage circuit configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value, the data storage circuit being further configured to store a data storage status indicator and address information associated with the read data; an address matching circuit configured to compare received address information with the address information stored in the data storage circuit in response to a received second command; and a management circuit configured to set the data storage status indicator if the received address information matches the stored address information.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory device. The memory device includes: an error correction circuit configured to correct errors in data read from a memory cell in response to the first command; and a data output circuit configured to output the corrected data in response to the second command.

At least one other example embodiment provides a memory system including: a memory controller configured to output a first command; and a memory device. The memory device includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; a data storage circuit configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value; and an error correction circuit configured to correct the stored data.

At least one other example embodiment provides a memory system including: a memory controller configured to output a first command; and a memory device. The memory device includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; and a correction status information generator configured to output correction status information associated with the read data, the correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory device. The memory device include: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; a data storage circuit configured to store the read data for error correction if the detected number of error bits is greater than or equal to a first threshold value; a management circuit configured to check a data storage status indicator in response to the second command, the data storage status indicator indicating whether the read data is stored in the data storage circuit; and a data output circuit configured to output one of corrected data from the data storage circuit and second data from the memory cell based on the data storage status indicator.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory device. The memory device includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; a data storage circuit configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value, the data storage circuit being further configured to store a data storage status indicator and address information associated with the read data; an address matching circuit configured to compare received address information with the address information stored in the data storage circuit in response to the second command; and a management circuit configured to set the data storage status indicator if the received address information matches the stored address information.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory chip coupled to the memory controller, the memory chip having an error correction apparatus. The error correction apparatus includes: an error correction circuit configured to correct errors in data read from a memory cell in response to the first command; and a data output circuit configured to output the corrected data in response to the second command.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory chip coupled to the memory controller, the memory chip having an error correction apparatus. The error correction apparatus includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; a data storage circuit configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value; and an error correction circuit configured to correct the stored data.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory chip coupled to the memory controller, the memory chip having an error correction apparatus. The error correction apparatus includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; and a correction status information generator configured to output correction status information associated with the read data, the correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory chip coupled to the memory controller, the memory chip having an error correction apparatus. The error correction apparatus includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; a data storage circuit configured to store the read data for error correction if the number of error bits is greater than or equal to a first threshold value; a management circuit configured to check a data storage status indicator in response to the second command, the data storage status indicator indicating whether the read data is stored in the data storage circuit; and a data output circuit configured to output one of corrected data from the data storage circuit and second data from the memory cell based on the data storage status indicator.

At least one other example embodiment provides a memory system including: a memory controller configured to output first and second commands; and a memory chip coupled to the memory controller, the memory chip having an error correction apparatus. The error correction apparatus includes: an error detector configured to detect a number of error bits in data read from a memory cell in response to the first command; a data storage circuit configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value, the data storage circuit being further configured to store a data storage status indicator and address information associated with the read data; an address matching circuit configured to compare received address information with the address information stored in the data storage circuit in response to the second command; and a management circuit configured to set the data storage status indicator if the received address information matches the stored address information.

At least one other example embodiment provides a method of operating a memory controller, the method including: outputting a first command to read first data; and outputting a second command to read an error corrected portion of the first data.

At least one other example embodiment provides a method of operating a memory device, the method including: correcting errors in data read from a memory cell in response to a first command; and outputting the corrected data in response to a second command.

At least one other example embodiment provides a method of operating a memory device, the method including: detecting a number of error bits in data read from a memory cell in response to a first command; storing the read data if the detected number of error bits is greater than or equal to a first threshold value; and correcting the stored data.

At least one other example embodiment provides a method of operating a memory device, the method including: detecting a number of error bits in data read from a memory cell in response to a received command; and outputting error correction status information associated with the read data, the error correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value.

At least one other example embodiment provides a method of operating a memory device, the method including: detecting a number of error bits in data read from a memory cell in response to a first command; storing the read data for error correction in a data storage circuit if the number of error bits is greater than or equal to a first threshold value; checking a data storage status indicator in response to a second command, the data storage status indicator indicating whether the read data is stored in the data storage circuit; and outputting one of corrected data and second data from the memory cell based on the data storage status indicator.

At least one other example embodiment provides a method of operating a memory device, the method including: detecting a number of error bits in data read from a memory cell in response to a first command; storing the read data, a data storage status indicator and address information associated with the read data if the detected number of error bits is greater than or equal to a first threshold value; comparing received address information with the stored address information in response to a received second command; and setting the data storage status indicator if the received address information matches the stored address information.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments of inventive concepts are shown. However, example embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of inventive concepts to those skilled in the art.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention. As used herein, the term “and/or,” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “connected,” or “coupled,” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected,” or “directly coupled,” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between,” versus “directly between,” “adjacent,” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

Specific details are provided in the following description to provide a thorough understanding of example embodiments. However, it will be understood by one of ordinary skill in the art that example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams in order not to obscure the example embodiments in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.

Also, it is noted that example embodiments may be described as a process depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations may be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. A process may be terminated when its operations are completed, but may also have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or the main function.

Moreover, as disclosed herein, the term “buffer,” “memory” or the like, may represent one or more devices for storing data, including random access memory (RAM), magnetic RAM, core memory, and/or other machine readable mediums for storing information. The term “storage medium” may represent one or more devices for storing data, including read only memory (ROM), random access memory (RAM), magnetic RAM, core memory, magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other machine readable mediums for storing information. The term “computer-readable medium” may include, but is not limited to, portable or fixed storage devices, optical storage devices, and various other mediums capable of storing or containing instruction(s) and/or data.

Furthermore, example embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine or computer readable medium such as a storage medium. A processor(s) may perform the necessary tasks.

A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

As process scaling of semiconductor memory devices continues, bit error rates (BERs) of memory cells increases. For example, a dynamic random access memory (DRAM) is a memory device having finite data retention characteristics, and as process scaling of a DRAM continues, a capacitance of a cell capacitor decreases, which increases BER and may decrease data reliability. According to example embodiments, an error correction circuit configured to correct error bits is included in a semiconductor memory device, and thus, more stable operation of the semiconductor memory device may be secured even at relatively high BERs.

is a block diagram illustrating a memory systemincluding a semiconductor memory device according to an example embodiment.

As illustrated in, the memory systemincludes a memory controllerand a semiconductor memory device. The memory controllerprovides various control signals to the semiconductor memory deviceto control memory operations. For example, the memory controllerprovides a command CMD and an address ADD to the semiconductor memory deviceto access data of a cell array. The command CMD may be a command related to various memory operations such as data read/write operation. When the semiconductor memory deviceincludes a DRAM cell, for example, the command CMD may include a command for various unique operations to a DRAM, such as a refresh command for refreshing a memory cell. While not illustrated in, other signals related to memory operations (e.g., a masking signal for masking data or a clock signal for synchronizing a memory operation) may be transmitted or received between the memory controllerand the semiconductor memory device.

According to at least one example embodiment, the memory controlleris configured to output a first command to read first data from the memory device, and to output a second command to read an error corrected portion of the first data from the memory device. The memory controller may include a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data.

Still referring to, the semiconductor memory deviceincludes a cell arrayincluding a plurality of memory cells, an error correction circuit (ECC) circuitto correct errors with respect to data read from the cell array, and a storage circuit(or data storage circuit) to temporarily store the read data. The data storage circuitmay be formed of various volatile or non-volatile memory circuits capable of storing various types of information. In one example, the data storage circuitmay be a buffer or a register. The data storage circuitdescribed below may store data information, address information, and various flag information. As discussed herein, a storage circuit or data storage circuit may sometimes be referred to as a data buffer.

The cell arrayincludes a plurality of regions, which may be defined in various forms. For example, the regions may be defined as page sizes selected in response to a row address or sizes in error correction circuits. The size of the regions may vary according to a structure of the cell array. For example, when the regions are defined in error correction circuits, at least two regions may be included in each page.

The ECC circuitmay perform various functions related to error detection and correction. In one example, the ECC circuitgenerates a parity bit via an ECC encoding operation when a data write operation is performed, and corrects error bits generated in read data via an ECC decoding operation. The ECC circuitmay include an ECC encoder (not shown) that generates a parity bit, an error detector (not shown) that detects the number of error bits generated in read data (or a code word including data and a parity bit), and an error correction circuit (not shown) that corrects error bits.