Pixel and display device including the same

More than one reissue application has been filed for the reissue of U.S. Pat. Ser. No. 10,482,821. The reissue applications include U.S. Pat. No. RE50,143, filed on Apr. 6, 2023 and published on Sep. 24, 2024, and the present continuation reissue application (U.S. patent application Ser. No. 18/891,117), filed on Sep. 20, 2024.

This applicationis a continuation reissue of U.S. patent application Ser. No. 18/131,368, filed on Apr. 6, 2023, which is a reissue of U.S. Pat. No. 10,482,821, filed on Jul. 13, 2018 as U.S. patent application Ser. No. 16/034/259 and issued on Nov. 19, 2019, andclaims priority from and the benefit of Korean Patent Application No. 10-2017-0167818, filed Dec. 7, 2017, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Exemplary embodiments generally relate to display devices, and more particularly, to pixels capable of compensating threshold voltages of driving transistors and display devices including the pixels.

Each pixel of an organic light emitting display device typically includes a light emitting element (e.g., an organic light emitting diode), a luminance of which varies according to a driving current. Each pixel may further include a driving transistor that controls an amount of the driving current supplied to the organic light emitting diode according to a data voltage, and a switching transistor that applies the data voltage to the driving transistor to control the luminance of the organic light emitting diode.

Driving transistors of the pixels may have different threshold voltages due to manufacturing idiosyncrasies and/or errors, and thus, even when the same data voltage is applied, the amount of driving current output from the driving transistors may be different according to the different threshold voltages, which results in luminance deviations among the pixels. To address this issue, various pixel circuits have been researched to compensate the threshold voltages of the driving transistors. For example, the pixel circuit may be driven in a frame period including an initialization period, a data writing and threshold voltage compensation period, and an emission period. As a resolution of the display device increases, the threshold voltage compensation period for compensating the threshold voltages of the driving transistors may be shortened, and thus, image quality may be degraded.

The above information disclosed in this section is only for understanding the background of the inventive concepts, and, therefore, may contain information that does not form prior art.

Some exemplary embodiments provide a pixel capable of improving image quality.

Some exemplary embodiments provide a display device including a pixel capable of improving image quality.

Additional aspects will be set forth in the detailed description which follows, and, in part, will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

According to some exemplary embodiments, a pixel includes first to fifth transistors, first and second capacitors, and a light emitting element. The first transistor includes a gate connected to a first node, a first terminal, and a second terminal connected to a second node. The second transistor includes a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node. The third transistor includes a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node. The fourth transistor includes a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node. The fifth transistor includes a gate configured to receive the first gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor. The first capacitor includes a first electrode connected to the first node, and a second electrode connected to the second node. The second capacitor includes a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage. The light emitting element includes a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.

In some exemplary embodiments, the second transistor may be configured to turn on in response to a first logic level of the first gate signal, and the fifth transistor may be configured to turn on in response to a second logic level of the first gate signal, the second logic level being different from the first logic level.

In some exemplary embodiments, the second transistor may be an n-channel metal oxide semiconductor (MOS) transistor, and the fifth transistor may be a p-channel MOS transistor.

In some exemplary embodiments, the third transistor and the fourth transistor may be n-channel MOS transistors.

In some exemplary embodiments, the first power supply voltage may be greater than the reference voltage, the initialization voltage, and the data voltage.

In some exemplary embodiments, the second transistor may be configured to receive the data voltage through a data line, and the third transistor may be configured to receive the reference voltage through a reference voltage line different from the data line.

In some exemplary embodiments, the reference voltage may be greater than the initialization voltage.

In some exemplary embodiments, the first transistor may further include a second gate connected to the second node.

In some exemplary embodiments, the first transistor may be an n-channel MOS transistor.

According to some exemplary embodiments, a display device includes a display panel including a plurality of pixels, and a panel driver configured to drive the display panel. At least one pixel among the pixels includes first to fifth transistors, first and second capacitors, and a light emitting element. The first transistor includes a gate connected to a first node, a first terminal, and a second terminal connected to a second node. The second transistor includes a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node. The third transistor includes a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node. The fourth transistor includes a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node. The fifth transistor includes a gate configured to receive the first gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor. The first capacitor includes a first electrode connected to the first node, and a second electrode connected to the second node. The second capacitor includes a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage. The light emitting element includes a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.

In some exemplary embodiments, a frame period of the display device may include: a first period in which the first node and the second node are initialized; a second period in which a threshold voltage of the first transistor is sensed; a third period in which the data voltage is applied to the first transistor; and a fourth period in which the light emitting element emits light based on the data voltage.

In some exemplary embodiments, a length of the second period may be longer than one horizontal period.

In some exemplary embodiments, a length of the third period may be one horizontal period.

In some exemplary embodiments, in the first period: the third transistor, the fourth transistor, and the fifth transistor may be configured to be turned on; and the second transistor may be configured to be turned off.

In some exemplary embodiments, in the second period: the third transistor and the fifth transistor may be configured to be turned on; and the second transistor and the fourth transistor may be configured to be turned off.

In some exemplary embodiments, in the third period: the second transistor may be configured to be turned on; and the third transistor, the fourth transistor and the fifth transistor may be configured to be turned off.

In some exemplary embodiments, in the fourth period: the fifth transistor may be configured to be turned on; and the second transistor, the third transistor, and the fourth transistor may be configured to be turned off.

In some exemplary embodiments, the second transistor may be an n-channel metal oxide semiconductor (MOS) transistor; and the fifth transistor may be a p-channel MOS transistor.

In some exemplary embodiments, the second transistor may be configured to receive the data voltage through a data line; and the third transistor may be configured to receive the reference voltage through a reference voltage line different from the data line.

In some exemplary embodiments, the first transistor may further include a second gate connected to the second node.

According to some exemplary embodiments, a pixel includes first to fifth transistors, first and second capacitors, and a light emitting element. The first transistor includes a gate connected to a first node, a first terminal, and a second terminal connected to a second node. The second transistor includes a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node. The third transistor includes a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node. The fourth transistor includes a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node. The fifth transistor includes a gate configured to receive a fourth gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor. The first capacitor includes a first electrode connected to the first node, and a second electrode connected to the second node. The second capacitor includes a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage. The light emitting element includes a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.

The first transistor may be a double gate transistor.

The first transistor may further include a second gate connected to the second node.

The second gate of the first transistor may be under an active layer of the first transistor.

The first power supply voltage may be higher than the reference voltage and the initialization voltage.

The reference voltage may be higher than the initialization voltage.

The first, second, third, fourth and fifth transistors may be n-channel MOS transistors.

The second transistor may be configured to receive the data voltage through a data line, and the third transistor may be configured to receive the reference voltage through a reference voltage line different from the data line.

A frame period may include a first period in which the first node and the second node are initialized, a second period in which a threshold voltage of the first transistor is sensed, a third period in which the data voltage is applied to the first transistor, and a fourth period in which the light emitting element emits light based on the data voltage.

The length of the second period may be longer than a length of the third period.

The length of the second period may be three to ten times as long as the length of the third period.

The length of the second period may be longer than one horizontal period.

The length of the third period may be one horizontal period.

In the first period, the third transistor and the fourth transistor may be configured to be turned on, and the second transistor may be configured to be turned off.

In the second period, the third transistor and the fifth transistor may be configured to be turned on, and the second transistor and the fourth transistor may be configured to be turned off.

In the third period, the second transistor may be configured to be turned on, and the third transistor, the fourth transistor and the fifth transistor may be configured to be turned off.

In the fourth period, the fifth transistor may be configured to be turned on, and the second transistor, the third transistor, and the fourth transistor may be configured to be turned off.

The second transistor may be an n-channel metal oxide semiconductor (MOS) transistor, and the fifth transistor may be a p-channel MOS transistor.

The first, second, third, fourth and fifth transistors may be p-channel MOS transistors.

The first power supply voltage may be a low power supply voltage, and the second power supply voltage may be a high power supply voltage.

According to various exemplary embodiments, a pixel may receive a data voltage through a data line, and may receive a reference voltage independently of the data voltage through a reference voltage line. In this manner, a threshold voltage sensing period of a pixel may be separated from a data writing period and a gate signal may be adjusted such that the threshold voltage sensing period has a sufficient length, and, as such, the length of the threshold voltage sensing period may be set longer than one horizontal period (e.g., 10 horizontal periods (10H)). Therefore, the pixel may prevent or at least reduce image quality degradation typically caused in a relatively high resolution display device and/or a display device driven with a relatively high frequency.