Semiconductor device for short-circuiting nodes connected to a word line control circuit and control method for the same

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2009-152642, filed Jun. 26, 2009; the entire contents of which are incorporated herein by reference.More than one reissue application has been filed for the reissue of U.S. Pat. No. 8,493,786. The reissue applications are the present reissue continuation application and application Ser. No. 16/041,428, filed Jul. 20, 2018, now RE49,175, which is a continuation of U.S. application Ser. No. 14/657,249, filed Mar. 13, 2015, now RE47,017, each of which is an application for reissue of U.S. Pat. No. 8,493,786, issued Jul. 23, 2013, which claims priority of Japanese Patent Application No. 2009-152642, filed Jun. 26, 2009, the entire contents of each application are incorporated herein by reference.

Embodiments described herein related generally to a semiconductor device applied to a nonvolatile semiconductor memory device.

RecentlyIn recent years, the distances between adjacent word lines and between adjacent bit linesare more narrowhave decreasedasthe device issemiconductor devices have becomefurther miniaturized.That isIn other words, the distance between memory cell transistorsis narrowhas been decreasing and is expected to continue to decrease. Therefore, for example,ifwhen binarydata is written into a memory cell transistor in which binary data isalreadyheld, the threshold distribution ofa memory cellthetransistorin which data has been already written varieswill varydue tovariationvariationsin the threshold distribution ofaan adjacentmemory cell transistoradjacent to the above memory cell transistor. In the following description,thevariation in the threshold distribution is referred to as a“coupling effect”.

Therefore, the threshold value of the memory cell transistor is raised from the initialreadvoltagelevel and it becomes necessary to transfer a higher voltage in order to turn on the memory cell transistor. That is, a voltage generator circuit that generates pluralvoltagesvoltage levelsis required.InJpn. Pat. Appln. KOKAI Publication No. H11-134892,describesvoltage generator circuitswhosewith varyingcurrent supply ratesare different are described.

In this case,if the abovewhen ahigh voltage is transferred to the control gate of a memory cell transistor adjacnet toaanothermemory cell transistor before the high voltage is transferred to the control gate of the latter memory cell transistor, gate induced drain leakage (GIDL) will occur between the impurity diffusion layer and the memory cell transistor.

Next, a first embodiment is explained with reference to the accompanying drawings. In the explanation, common reference symbols are attached to common portions throughout the drawings.

In general, according to one embodiment, a semiconductor device includes a first voltage generator circuit, a second voltage generator circuit, a first MOS transistor, and a controller. The first voltage generator circuit outputs a first voltage to a first node. The second voltage generator circuit outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first and second nodes. The controller performs a control operation to short-circuit the first and second nodes by turning on the first MOS transistor. The controller controls atimeperiod in which the first MOS transistor is kept in the on statebased on time.

[First Embodiment]

The semiconductor device according to the first embodiment is explained with reference to. Thesummarysemiconductor deviceof this embodiment isconfiguredto short-circuit the output terminals of two or more voltage generator circuits thateachgenerate various voltages at atime of areadtimeoperation. Therefore,voltage transfer timingstimingof voltages applied to plural word lines WL are set to the same timing. First, the configuration of the semiconductor device according to the first embodiment is explained.

In,showsthe semiconductor device according to the first embodimentis shown. As one example, a NAND flash memory is provided. As shown in, the NAND flash memory includes a memory cell array,arow decoder,aword line control circuit,avoltage generator circuit,asense amplifierandacontroller. First, the memory cell arrayis explained.

<Configuration Example of Memory Cell Array>

As shown in, the memory cell arrayincludes plural blocks BLKto BLKs (s is a natural number). Each of the blocks BLKto BLKs includes plural NAND stringsincluding nonvolatile memory cell transistors MT serially connected.

For example, each of the NAND stringsincludes 64 memory cell transistors MT and select transistors ST, ST. The memory cell transistor MT hasana floating gate (FG)structure having a charge storage layer (for example, conductive film) formed above a semiconductor substrate with a gate insulating film disposed therebetween, an inter-level insulating film formed on the charge storage layer and a control gate electrode formed on the inter-level insulating film.

The number of memory cell transistors MT is not limited to 64 and may be set to 128, 256 or 512and the number is not limitative, or other multiple of 64. Further, adjacent ones of the memory cell transistors MTcommonlyhavethea commonsource or drain. The memory cell transistors MT are arranged to have the current paths serially connected between the select transistors STand ST. The drain region on one-end side of the series-connected memory cell transistors MT is connected to the source region of the select transistor STand the source region on the other end side is connected to the drain region of the select transistor ST.

The charge storage layer of the memory cell transistor may be formed of a conductive film (floating gate) such as a polysilicon film, for example, but may be formed of an insulating film (MONOS structure). Inthisthe lattercase, the laminated gate includes a charge storage layer formed of an insulating film on the gate insulating film, a block layer formed of a ferroelectric material having a dielectric constant higher than that of the charge storage layer on the charge storage layer and a control gate formed on the block layer.

The control gate of the memory cell transistor MT functions as a word line WL, the drainof the control gateis electrically connected to a bit line BL and the sourceof the control gateis electrically connected to a source line SL.

The control gate electrodes of the memory cell transistors MT arranged on the same row are commonly connected to a corresponding one of word lines WLto WLand the gate electrodes of the select transistors ST, STarranged on the same row are commonly connected to select gate lines SGD, SGS, respectively. Forsimplifying the explanation, inease of understanding ofthe following explanation, the word lines WLto WLmay simply be referred to as word lines WL if they are not separately used. Further, the drains of the select transistors STarranged on the same column in the memory cell arrayare commonly connected to a corresponding one of bit lines BLto BLn. In the following description, the bit lines BLto BLn are referred to as bit lines BL if they are not separately used (n is a natural number). The sources of the select transistors STare commonly connected to the source line SL.

Further,during operationdata is simultaneously written into the plural memory cell transistors MT connected to the same word line WLand the. Aunit of thepluralmemory cell transistors is called a page. Further, data items of the plural NAND stringsare simultaneously erased in the block BLK unit.

<Cross-Sectional View of Memory Cell Array>

Next, the cross section of the memory cell arrayin the blocks BLKto BLKs with the above configuration is explained with reference to.is a cross-sectional view of the NAND stringtaken along the bit line BL direction in.

As shown in, an n-type well regionis formed in the surface area of a p-type semiconductor substrate. A p-type well regionis formed in the surface area of the n-type well region. A gate insulating filmis formed on the p-type well region. Gate electrodes of memory cell transistors MT and select transistors ST, STare formed on the gate insulating film.

The gate electrodes of the memory cell transistors MT and select transistors ST, STare formed with the laminated structure having an FG structure. The laminated structure is obtained by sequentially forming a conductive film, inter-level insulating filmand polysilicon layeron the gate insulating film. The surface portion of the polysilicon layeris modified into a metal silicide form.

In the memory cell transistor MT explained above, the gate insulating filmfunctions as a tunnel insulating film. The conductive filmfunctions as a floating gate (FG) and the polysilicon layerfunctions as a control gate. The polysilicon layersthat are adjacentto each otherin the word line WL direction intersecting with the bit line BL direction inare commonly connectedto each of the bit lines BLandeach of the polysilicon layers 107function as a control gate electrode (word line WL). In the following description, the conductive filmand polysilicon layermay be referred to as a charge storage layerand control gate, respectively.

Further, in the select transistors ST, ST, the conductive filmsthatare adjacentto each otherin the word line WL directionandarecommonlyconnectedin common. Then, the conductive filmsfunction as select gate lines SGS, SGD. At this time, only the polysilicon layermay function as a select gate line. In this case, the potentials of the polysilicon layersof the select transistors ST, STare set at a constant potential or set into a floating state.

In portions of the surface area of the p-well regionthat lie between the gate electrodes, n-type impurity diffusion layersare formed. The n-type impurity diffusion layeris commonly used by the adjacent transistors and functions as a source (S) or drain (D). Further, a region between the adjacent source and drain functions as a channel region used as an electron moving region. The gate electrodes, n-type impurity diffusion layersand channel regionsconfigureformtransistors used as the memory cell transistors MT and select transistors ST, ST.

On the p-type semiconductor substrate, an inter-level insulating filmis formed to cover the memory cell transistors MT and select transistors ST, ST. In the inter-level insulating film, a contact plug CPthat reaches the n-type impurity diffusion layer (source)of the select transistor STon the source side is formed. In the surface area of the inter-level insulating film, a metal interconnection layerconnected to the contact plug CPis formed. The metal interconnection layerfunctions as a part of the source line SL. In the inter-level insulating film, a contact plug CPthat reaches the n-type impurity diffusion layer (drain)of the select transistor STon the drain side is formed. A metal interconnection layerconnected to the contact plug CPis formed in the inter-level insulating film. An inter-level insulating filmis formed on the inter-level insulating film. An inter-level insulating filmis formed on the inter-level insulating film. A metal interconnection layeris formed on the inter-level insulating film. The metal interconnection layerfunctions as a bit line BL. A contact plug CPwhose upper surface contacts with the metal interconnection layerand whose bottom surface contacts with the metal interconnection layeris formed in the inter-level insulating films,. The contact plugs CP, CPand metal interconnection layerfunction as a contact plug CP. Further, an insulating filmis formed on the metal interconnection layer.

<Threshold Distribution of Memory Cell Transistor MT>

Next, the threshold distribution of the memory cell transistor MT is explained with reference to.is a graph showing the threshold distribution on the abscissa and the number of cells of the memory cell transistors MT on the ordinate.

As shown in, each of the memory cell transistors MT can hold binary (2-level) data (one-bit data), for example. That is, the memory cell transistor MT can hold two types of data items of “1” and “0” in an order starting from the lowest threshold voltage Vth.

The threshold voltage Vthof “1” data in the memory cell transistor MT is set to satisfy the relationship of Vth<V. The threshold voltage Vthof “0” data is set to satisfy the relationship of V<Vth. Thus, the memory cell transistor MT can hold 1-bit data of “0” data and “1” data according to the threshold voltage.

The threshold voltage varies by injecting charges into the charge storage layer. Further, the memory cell transistor MT may be formed to hold data of four or more values.

<Row Decoder>

Next, the row decoderis explained with referencebacktoagain. The row decoderincludes a block decoderand n-channel MOS transistorsto. The block decoderdecodes a block address supplied from the controllerat thetime of adata write operationtime,time of aread operationtimeandtime of anerasetimeoperation. Then, the block decoderselects one of the blocks BLK based on the decoded result. That is, the block decoderselects the MOS transistorstocorresponding to the block BLK that contains the selected memory cell transistor MT and turns on the MOS transistorstovia a control line TG.

At this time, a block select signal is output from the block decoder. The block select signal is a signal used to permit the row decoderto select one of the plural memory blocks BLKto BLKs at thetime of adata readtimeoperation,time of awritetimeoperationora time of anerasetimeoperation. As a result, the row decoderselects the row direction of the memory cell arraycorresponding to the selected block BLK. That is, the row decoderapplies voltages supplied from the voltage generator circuitvia the word line control circuitto the select gate lines SGD, SGSand word lines WLto WLbased on the select signal supplied from the block decoder.

<Word Line Control Circuit>

Next, the word line control circuitis explained. In this case, the function of the word line control circuitis explained. The word line control circuittransfers various voltages generated from the voltage generator circuittoadequaterespectiveword lines WL assigned by the row decodervia the row decoder.

For example, it issupposedassumedthat the memory cell transistor MT to be read is connected to the word line WL. In this case, the word line control circuittransfers a voltage corresponding to read data held by the memory cell transistor MT to the word line WL. Then, the word line control circuitperforms a control operation to transfer a voltage that turns on the memory cell transistor MT to the word lines WLto WLand word lines WLto WLother than the word line WL.

A signal sgd is transferred to the gate of the select transistor STvia the select gate line SGDby means of the word line control circuit. Further, a signal sgs is transferred to the gate of the select transistor STvia the select gate line SGSby means of the word line control circuit. Each of the signal sgd and signal sgs is a signal in which the ‘H’ level is set to voltage VDD (for example, 1.8 [V]) and the ‘L’ level is set to 0 [V]. The select transistors ST, STare turned on by voltage VDD.

<Voltage Generator Circuit>

Next, the voltage generator circuitis explained. As shown in, the voltage generator circuitincludes a first voltage generator circuit, second voltage generator circuit, third voltage generator circuit, fourth voltage generator circuitand fifth voltage generator circuit. The first voltage generator circuitto fifth voltage generator circuitare explained with reference to.

As shown in, each of the first voltage generator circuitto fifth voltage generator circuitincludes a limiter circuitand charge pump circuit. The charge pump circuitgenerates voltages required for performing, for example, the data write operation, erase operation and read operation that are controlled by the controller. Each voltage thus generated is output from the node Nand supplied to, for example, the row decoderof the NAND flash memory via the word line control circuit.

The limiter circuitcontrols the charge pump circuitaccording to the potential of the node Nmonitoring the potential of the node N. That is, the limiter circuitstops the pumping operation of the charge pump circuitto drop the potential of the node Nif the potential of the node Nis higher than a preset potential.

On the other hand, if the potential of the node Nis lower than the preset potential, the limiter circuit instructs the charge pump circuitto perform the pumping operation to raise the potential of the node N.

Next, voltages generated from the first voltage generator circuitto fifth voltage generator circuitare explained. The first voltage generator circuitgenerates voltage VREAD and transfers voltage VREAD to unselected word lines at thetime of adata readtimeoperation. Voltage VREAD is a voltage used to turn on the memory cell transistor MT irrespective of data to be held.

The second voltage generator circuitgenerates voltage VREADLA. Voltage VREADLA generated from the second voltage generator circuitis transferred to the unselected word line WL adjacent to the drain side of the selected word line WL via the row decoder. Like voltage VREAD, voltage VREADLA is a voltage used to turn on the memory cell transistor MT connected to the unselected word line WL and is set higher than voltage VREAD as required. That is, voltage VREADLA may be set lower than voltage VREAD. The magnitude of voltage VREADLA is controlled by the limiter circuit.

The third voltage generator circuitgenerates voltage VCGR at thetime of adata readtimeoperation. Voltage VCGR is transferred to the selected word line WL. Voltage VCGR is a voltage corresponding to data to be read from the memory cell transistor MT.

The fourth voltage generator circuitgenerates voltage VPGM at thetime of adata writetimeoperationand transfers voltage VPGM to the selected word line WL. Voltage VPGM is a voltage with such magnitude that injects charges of the channel in the memory cell transistor MT into the charge storage layer and the shifts threshold voltage of the memory cell transistor MT to another level.

The fifth voltage generator circuitgenerates voltage VPASS and transfers voltage VPASS to the unselected word lines WL. Voltage VPASS is a voltage used to turn on the memory cell transistor MT. If the first voltage generator circuitto fifth voltage generator circuitare not separately used, they are simply referred to as the voltage generator circuit.

<Sense Amplifier>

The sense amplifiersenses and amplifies data of the memory cell transistor MT read to the bit line BL at thetime of adata readtimeoperation. More specifically, the sense amplifierprecharges the bit line BL to voltage VDD. Then, the sense amplifiersenses a voltage (or current) of the bit line BL.