Input receiver circuits selectively connected to input/output pad based on operation mode

This application isa reissue application of U.S. Pat. No. 9,934,169, and is a divisional of U.S. application Ser. No. 16/838,536 (now reissued as U.S. Pat. No. RE49,506), which is also an application for reissue of U.S. Pat. No. 9,934,169, which issued on Apr. 3, 2018 on U.S. application Ser. No. 15/416,565 filed Jan. 26, 2017, which wasa continuation of U.S. application Ser. No. 14/818,586, filed on Aug. 5, 2015, which was a continuation of U.S. application Ser. No. 14/093,916 filed Dec. 2, 2013 which claims priority under 35 U.S.C. § 119(e) to U.S. provisional patent application No. 61/732,589 filed on Dec. 3, 2012, and under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2013-0028039 filed on Mar. 15, 2013, the entire contents of each of which are hereby incorporated by reference in their entirety.

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 9,934,169. The three reissue applications are U.S. application Ser. Nos. 18/168,814 (the present application), 16/838,536, and 16/838,573, all of which are reissues of U.S. Pat. No. 9,934,169.

Embodiments of the present inventive concepts relate to a method of operating input/output interfaces, and more particularly to a method of operating an input/output interface which may select and use one of a plurality of output driver circuits or one of a plurality of input receiver circuits.

Each of a system on chip (SoC) including a central processing unit (CPU) and a memory controller and a memory device (e.g., main memory), connected to the SoC includes an input/output interface for interfacing mutual data transmission.

According to an increased operation speed, as a swing width of a data signal mutually transmitted and received between the SoC and the memory device gets decreased, not only an influence of external noise gets increased, but also impedance mismatching in the input/output interface may be a problem. In order to solve the impedance mismatching, the input/output interface may include an impedance mismatching circuit which is referred to as On-Die Termination, On-Chip Termination, or On-Board Termination.

According to an example embodiment of the inventive concepts, a method of operating an input/output interface is provided. The method may include selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected output driver circuit. The mode selection signal is a control signal for controlling an on-die termination (ODT) circuit included in the input/output interface.

Example embodiments provide that the method may further include generating the mode selection signal according to a memory latency before the selecting.

Example embodiments provide that the memory latency may be a read latency or a write latency.

Example embodiments provide that the method may further include generating the mode selection signal based on a mode register set (MRS) command before the selecting. The MRS command may be used for adjusting an operation frequency.

Example embodiments provide that the selecting may select one of the plurality of output driver circuits which includes a NMOS pull-up transistor when the mode selection signal indicates an operation mode for a high speed operation, and one of the plurality of output driver circuits which includes a PMOS pull-up transistor when the mode selection signal indicates an operation mode for a low speed operation.

Example embodiments provide that the method may further include selecting one of a plurality of termination levels of the ODT circuit included in the input/output interface according to the mode selection signal.

Example embodiments provide that the plurality of termination levels may include a supply voltage level, a ground voltage level, and a medium level between the supply voltage level and the ground voltage level.

According to an example embodiment of the inventive concepts, a method of operating an input/output interface is provided. The method may include selecting one of a plurality of input receiver circuits according to a mode selection signal, and receiving a data signal input using the selected input receiver circuit.

Example embodiments provide that the mode selection signal may be a control signal for controlling the on-die termination (ODT) circuit included in the input/output interface.

Example embodiments provide that the method may further include generating the mode selection signal according to memory latency before the selecting, and the memory latency may include a read latency and write latency.

Example embodiments provide that the method may further include generating the mode selection signal based on a mode register set (MRS) command, the MRS command may be used for adjusting a memory operation frequency before the selecting.

Example embodiments provide that the selecting may select a different input receiver circuit when the mode selection signal indicates an operation mode for a high speed operation and than when the mode selection signal indicates an operation mode for a low speed operation.

Example embodiments provide that the selecting may select at least one of the plurality of input receiver circuits having a plurality of stages when the mode selection signal indicates an operation mode for a high speed operation.

Example embodiments provide that the selecting may select at least one of the plurality of input receiver circuits having different types of MOS transistors when the mode selection signal indicates an operation mode for a low speed operation, the different types of MOS transistors being connected to each other in series.

Example embodiments provide that the method may further include selecting one of a plurality of sense amplifier flip-flops according to the mode selection signal.

According to an example embodiment, a method of operating an input/output interface is provided. The method may include generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal.

Example embodiments provide that a controller of a memory device includes a mode register configured to store operation mode data for controlling the memory device, and the operation mode data includes memory latency data and operation frequency data. The memory latency data may indicate a memory latency of the memory device. The operation frequency data may indicate an operation frequency of the memory device.

Example embodiments provide that generating the mode selection signal is further based on the operation frequency data.

Example embodiments provide that generating the mode selection signal is further based on the memory latency data.

Example embodiment provide that the method may further include selecting one of a plurality of output driver circuits according to the mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits.

The inventive concepts now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

is a block diagram of a memory system according to an example embodiment of the inventive concepts. Referring to, a memory systemaccording to an example embodiment of the inventive concepts may include a memory device(e.g., a main memory) and a system on chip (SoC).

According to an example embodiment, the memory systemmay be embodied in a mobile application processor (AP); however, a technical scope of the inventive concepts is not limited thereto. In various embodiments, the memory systemmay be embodied in a special purpose AP and/or any other like AP.

The memory devicemay include a first internal circuitcomposing the inside of the memory deviceand a first input/output (I/O) interface. According to an example embodiment, the memory devicemay be embodied in a dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) and the like), and a technical scope of the inventive concepts is not limited thereto.

The first input/output interfacemay interface a data signal input or a data signal output between the first internal circuitand the SoC. The first internal circuitand the first input/output interfaceare described in detail referring to.

The memory devicemay be connected to the SoCthrough a bus. The SoCmay include a second internal circuitcomposing the inside of the SoCand a second input/output interface.

According to an example embodiment, the second internal circuitmay include a central processing unit (CPU) (not shown) for entirely performing an operation of the memory system, a graphic processing unit (GPU) (not shown), and/or a memory controller (not shown). According to an example embodiment, the second input/output interfacemay be included in the memory controller. A structure of the second internal circuitis substantially the same as a structure of the first internal circuit.

is a block diagram according to an example embodiment of a memory device illustrated in. Referring to, the first internal circuitof the memory devicemay include a control logic, a refresh counter, a row multiplexer, a plurality of row buffers, a plurality of row decoders, a bank control logic, a plurality of column buffers, a plurality of column decoders, a plurality of banks, and an input/output gate.

The control logicmay control each configuration element (e.g., the refresh counter, the row multiplexer, the bank control logic, and/or a plurality of column buffers) in response to a plurality of signals (a clock signal CK, a command signal CMD, and an address signal ADD).

The command signal CMD may denote a combination of a plurality of commands (e.g., CS, RAS, CAS, and/or WE). According to an example embodiment, the command signal CMD and the address signal ADD may be transmitted from a memory controller (not shown) included in the SoC.

The control logicmay include a command decoder-and a mode register-. According to an example embodiment, the command decoder-and/or the mode register-may be separately embodied outside the control logic. The command decoder-may decode a command signal CMD configured to have a plurality of signals (e.g., CS, RAS, CAS, and/or WE) based on a clock signal CK, and generate a command for controlling each configuration element (e.g., the refresh counter, the row multiplexer, the bank control logic, and/or the plurality of column buffers) according to a result of the decoding.

According to an example embodiment, the command decoder-may decode the command signal CMD, and generate a command for performing various types of operations (e.g., a read operation, a write operation, and/or a refresh operation).

The mode register-stores data for controlling various operation modes of the memory device. According to an example embodiment, the mode register-may store data about a memory latency of the memory device, data about an operation frequency, and/or data necessary for a control of the on-die termination (ODT) circuit (not shown).

The refresh counter, in response to a refresh command output from the command decoder-, may generate a row address corresponding to the refresh command.

The row multiplexermay select one of a row address generated by the refresh counterand a row address output from the control logicin response to a selection signal (not shown). According to an example embodiment, when a refresh operation is performed, the row multiplexermay select a row address generated by the refresh counter. According to another example embodiment, when a normal memory access operation (e.g., a read operation or a write operation), is performed, the row multiplexermay select a row address output from the control logic.

Each of the plurality of row decodersmay buffer a row address output from the row multiplexer. According to an example embodiment, the plurality of row decodersmay be embodied in a row decoder; however, example embodiments are not limited thereto.

A row decoder corresponding to a bank selected by the bank control logicamong the plurality of row decodersmay decode a row address output from a row buffer corresponding to the bank among the plurality of row buffers. According to an example embodiment, the plurality of row decodersmay be embodied in a row decoder; however, example embodiments are not limited thereto.

The bank control logicmay select at least one of the plurality of banksaccording to a control signal and/or command of the control logic.

Each of the plurality of column buffersmay buffer a column address output from the control logic. According to an example embodiment, the plurality of column buffersmay be embodied in one column buffer; however, example embodiments are not limited thereto. A column decoder corresponding to a bank selected by the bank control logicamong the plurality of column decodersmay decode a column address output from a column buffer corresponding to the bank among the plurality of column buffers.

According to an example embodiment, the plurality of column decodersmay be embodied in one column decoder; however, example embodiments are not limited thereto.

Each of the plurality of bankseach labeled as Bankto BankN may include a memory cell arrayand a sense amplifiers & write driver block.