Data storage device comprising dual channel preamp circuit

This application is an application for reissue of U.S. Pat. No. 10,896,695, which is incorporated herein by reference in its entirety.

Data storage devices such as disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and embedded servo sectors. The embedded servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo controller to control the velocity of the actuator arm as it seeks from track to track.

A disk drive typically comprises a plurality of disks each having a top and bottom surface accessed by a respective head. That is, the VCM typically rotates a number of actuator arms about a pivot in order to simultaneously position a number of heads over respective disk surfaces based on servo data recorded on each disk surface.shows a prior art disk formatas comprising a number of servo tracksdefined by servo sectors-recorded around the circumference of each servo track. Each servo sectorcomprises a preamblefor storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync markfor storing a special pattern used to symbol synchronize to a servo data field. The servo data fieldstores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sectorfurther comprises groups of servo bursts(e.g., N and Q servo bursts), which are recorded with a predetermined phase relative to one another and relative to the servo track centerlines. The phase based servo burstsprovide fine head position information used for centerline tracking while accessing a data track during write/read operations. A position error signal (PES) is generated by reading the servo bursts, wherein the PES represents a measured position of the head relative to a centerline of a target servo track. A servo controller processes the PES to generate a control signal applied to a head actuator (e.g., a voice coil motor) in order to actuate the head radially over the disk in a direction that reduces the PES.

shows a data storage device in the form of a disk drive according to an embodiment comprising an enclosurecomprising a first headactuated over a first disk surfaceand a second head(not shown) actuated over a second disk surface.is a flow diagram according to an embodiment wherein a manufacture printed circuit board (PCB)is coupled to the enclosure (block), wherein the manufacture PCBcomprises at least one dual channel configured to execute concurrent access operations. While the manufacture PCB is coupled to the enclosure, the data storage device is operated as a dual channel device (block). The manufacture PCBis decoupled from the enclosure and a product PCBis coupled to the enclosure (block), wherein the product PCB comprises a single channel configured to execute a single access operation. While the product PCB is coupled to the enclosure, the data storage device is operated as a single channel device (block).

In the embodiment of, each disk surface comprises a plurality of servo sectors-that define a plurality of servo tracks, wherein data tracksare defined relative to the servo tracks at the same or different radial density. Control circuitry processes a read signal emanating from the head to demodulate the servo sectors and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. A servo control system in the control circuitry filters the PES using a suitable compensation filter to generate a control signal applied to a VCMwhich rotates an actuator armabout a pivot in order to actuate the head radially over the disk in a direction that reduces the PES. In one embodiment, each head may also be servoed using a secondary actuator, such as a piezoelectric (PZT) actuator, configured to actuate a suspension relative to the actuator arm, and/or configured to actuate the head relative to the suspension. The servo sectors-may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern or a phase based servo pattern ().

shows a data storage device in the form of a disk drive wherein one or more disks, head stack assembly, and VCM such as shown inare installed into a base castingwhich is then sealed with a top cover (not shown) to form the enclosure. In this embodiment, the manufacture PCBshown inis coupled to a bottom of the base castingusing any suitable coupling features (e.g., clips), wherein the manufacture PCBcomprises a suitable interface connector for connecting to an interface cable (e.g., Serial ATA or SCSI). After executing manufacture procedures on the disk drive, the manufacture PCBmay be decoupled from the base casting(e.g., unclipped) and the product PCBcoupled to the base castingprior to shipping the data storage device to a customer.

In one embodiment, the enclosureshown inmay be a pluggable module configured to plug into a manufacture station comprising the manufacture PCB. After executing the manufacture procedures, the module may be shipped to a customer wherein the module may be plugged into a product device, such as plugging the module into a bay of a storage array, wherein the bay may comprise the product PCB.

Any suitable manufacture procedure may be executed by the manufacture PCB, wherein in one embodiment the data storage device is operated as a dual channel device during the manufacturing procedure meaning that at least two of the heads are concurrently accessing respective disk surfaces (e.g., concurrent writes, concurrent reads, or concurrent write/read). For example, the manufacture PCBmay execute a servo writing procedure wherein servo sectors (such as shown in) may be bank written to at least two disk surfaces in order to expedite the servo writing and/or to improve the coherency of the servo sectors across the disk surfaces. In another embodiment, the manufacture PCBmay execute a defect scan of the disk surfaces in order to map out defective data sectors, such as by writing/reading a test pattern to/from the disk surfaces and detecting a defect based on the read signal(s). In yet another embodiment, the manufacture PCBmay execute a manufacture procedure in order to measure the functionality of one or more components (e.g., a head component such as a write coil, a write assist element, a read element, a fly height actuator, a secondary actuator, etc.), or to measure a geometry of a head component, such as measuring a width of a write element, or measuring a radial and/or down-track offset between write/read elements and/or multiple read elements. Regardless as to the manufacture procedure executed, in one embodiment the manufacture PCBexecuting concurrent access operations using at least one dual channel may help facilitate and/or expedite the manufacture procedure. After having executed the manufacturing procedures, the product PCBmay be coupled to the enclosureand the data storage device operated as a single channel device. In this manner, the product PCBmay comprise fewer components compared to the manufacture PCB, thereby reducing the cost of the end product as well as reducing the manufacturing time of the data storage device.

shows a manufacture PCBaccording to an embodiment coupled to the enclosurethrough any suitable interface, such as an interface cable, plug-in connector, or wireless protocol (e.g., Wi-Fi). In this embodiment, the enclosurecomprises a first single channel preamp circuitcoupled to a first set of heads, such as headactuated over the top surface of a diskand headactuated over a bottom surface of the disk. The enclosurefurther comprises a second single channel preamp circuitcoupled to a second set of heads, such as headactuated over the top surface of a diskand headactuated over a bottom surface of the disk. In this embodiment, the manufacture PCBcomprises first manufacture control circuitrycoupled to the first preamp circuitand second manufacture control circuitrycoupled to the second preamp. Each of the manufacture control circuitryandmay comprise any suitable circuitry, such as read channel circuitry, servo control circuitry, a microprocessor configured to execute instructions stored on a computer readable medium, etc. When executing an access operation (write/read operation), the first manufacture control circuitryinterfaces with the first preamp circuitover interfacein order to select a target head out of the first set of heads as well as transmit a write signal during write operations and receive a read signal during read operations. Similarly, the second manufacture control circuitryinterfaces with the second preamp circuitover interfacein order to select a target head out of the second set of heads as well as transmit a write signal during write operations and receive a read signal during read operations. In one embodiment, a first access operation executed by the first manufacture control circuitryat least partially overlaps with a second access operation executed by the second control circuitryin order to execute any suitable manufacture procedure as described above, thereby operating the data storage device as a dual channel device.

shows a product PCBaccording to an embodiment coupled to the enclosurethrough any suitable interface, such as an interface cable, plug-in connector, or wireless protocol (e.g., Wi-Fi). In this embodiment, the product PCBcomprises product control circuitrycoupled to the first preamp circuitand to the second preampover interface. In one embodiment, the product control circuitrymay comprise any suitable circuitry, such as read channel circuitry, servo control circuitry, a microprocessor configured to execute instructions stored on a computer readable medium, etc. When executing an access operation (write or read), the product control circuitryselects a target head out of either the first set of heads or the second set of heads as well as transmits a write signal during write operations and receives a read signal during read operations. In this manner, the product control circuitryoperates the data storage device as a single channel device so as to reduce the cost of the product device by reducing the cost of the control circuitry as compared to the manufacture PCB.

In one embodiment, when executing concurrent operations the manufacture PCBmay execute concurrent access operations to top and bottom surfaces of a disk. For example, in one embodiment the manufacture PCBmay bank write servo sectors to the top and bottom surfaces in order to improve the coherency of the servo sectors. In this manner, when executing an access operation concurrently to top and bottom surfaces the coherency of the servo sectors enables the concurrent tracking of heads over the top and bottom surfaces. For example, the coherency of the servo sectors may enable the stroke of secondary actuators to track the deviations between top and bottom data tracks. In addition, the coherency of the servo sectors across the top and bottom surfaces may be substantially maintained in the event the disk is subject to thermal expansion or disk slip relative to a spindle of a spindle motor configured to rotate the disks.

shows an embodiment wherein the enclosurecomprises a first single channel preampcoupled to the top heads of the disks as well as coupled to the first manufacture control circuitryover interface. The enclosurefurther comprises a second single channel preampcoupled to the bottom heads of the disks as well as coupled to the second manufacture control circuitryover interface. The manufacture PCBexecutes a concurrent access operation by selecting a top head serviced by the first single channel preamp circuitand selecting a corresponding bottom head serviced by the second single channel preamp circuit.

In the embodiment of, there is an increased complexity in routing interface lines between the single channel preamp circuitsandand the top and bottom heads (e.g., using a flex cable). This increase in routing complexity as illustrated inis due to the interleaving of the interface lines between the first and second single channel preamp circuitsand. In one embodiment shown in, the routing complexity ofis avoided by using dual channel preamp circuitsand, wherein each dual channel preamp circuit is coupled to the manufacture control circuitryandover the interfaceand. The first dual channel preamp circuitis coupled to the top and bottom heads of a first set of disks (e.g., disk), and the second dual channel preamp circuitis coupled to the top and bottom heads of a second set of disks (e.g., disk). When executing a concurrent access operation, the manufacture PCBselects one of the first or second dual channel preamp circuits in order to concurrently access the top and bottom surfaces of a target disk. That is in this embodiment, each dual channel preamp circuit is capable of executing concurrent access operations to the top and bottom surfaces of a target disk, including to facilitate the concurrent transfer of write/read data to/from the manufacture PCBover the interfaceand. When the enclosureis coupled to the product PCB, the product control circuitryis coupled to the first and second dual channel preamp circuitsandsimilar to the embodiment shown in.

shows an example of a dual channel preamp circuitwherein the interface to the manufacture PCBincludes a selection controlfor selecting top and bottom heads of a target disk, as well as a write/read interface for the first channel and a write/read interface for the second channel. The write/read interfaces of each channel are applied to enable circuitsto, wherein each enable circuit (e.g., enable circuit) is coupled to the top and bottom heads of a respective disk (e.g., top headand bottom head). When executing a concurrent access operation, the selection controlis decoded by a decoderin order to activate the enable circuit of a target disk, thereby enabling the concurrent access operation using the corresponding top and bottom heads.

In one embodiment, the manufacture PCBmay comprise control circuitry capable of executing concurrent access commands to the top/bottom surfaces of multiple disks. That is in one embodiment, instead of the interfacesandbeing wire-ORed as shown in the embodiment of, in another embodiment the interfacesandmay be multiplexed between multiple control circuitry of the manufacture PCBso as to enable the concurrent access of top/bottom surfaces for a disk in the first set (corresponding to the first dual channel preamp circuit) and the top/bottom surfaces of a disk in the second set (corresponding to the second dual channel preamp circuit).

In the embodiments described above, the interface between the manufacture PCBor product PCBand the enclosuremay be implemented in any suitable manner. In one embodiment, the interface may comprise a parallel interface or a serial interface, or in another embodiment a combination of a parallel and a serial interface. For example, in one embodiment the write/read lines may be implemented using dedicated interface lines, whereas certain commands (e.g., the head selection command) may be transmitted to the preamp circuits over a serial interface. In yet another embodiment, the interface may comprise a wireless interface, such as a suitable Wi-Fi interface.

In one embodiment, the interface between the manufacture PCBor product PCBand the enclosuremay include control signals for controlling a primary actuator (e.g., a VCM) and one or more secondary actuators (e.g., a PZT) configured to actuate the heads radially over the disk surfaces. In one embodiment, the control signals for the secondary actuator(s) generated by the product PCBmay be effectively wire-ORed such as shown insuch that one of the heads may be actuated in fine movements while operating the data storage device as a single channel device.

In one embodiment after coupling the product PCBto the enclosure, the product control circuitrymay execute additional manufacturing procedures prior to shipping the data storage device to a customer. For example, in one embodiment the product control circuitrymay execute manufacturing procedures that verify the functionality of the product PCBas well as test and/or compensate for variations between the manufacture PCBand the product PCB. In other embodiments, the product PCBmay execute any suitable finishing manufacturing procedures, such as executing additional testing/calibration procedures, and/or writing operating system and/or calibration data to one or more of the disks.

In the embodiments described above, the storage medium of the data storage device is a disk, such as a magnetic disk. Other embodiments may employ other types of storage mediums, such as a magnetic tape. That is, the enclosureshown inmay comprise any suitable actuating mechanics configured to actuate write and read elements over any suitable storage medium, as well as optionally comprise one or more single channel and/or dual channel preamp circuits.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a data storage controller, or certain operations described above may be performed by a read channel and others by a data storage controller. In one embodiment, the read channel and data storage controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable power large scale integrated (PLSI) circuit implemented as a separate integrated circuit, integrated into the read channel or data storage controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry. In some embodiments, at least some of the flow diagram blocks may be implemented using analog circuitry (e.g., analog comparators, timers, etc.), and in other embodiments at least some of the blocks may be implemented using digital circuitry or a combination of analog/digital circuitry.

In various embodiments, a disk drive may include a magnetic disk drive, a hybrid disk drive comprising non-volatile semiconductor memory, a tape drive, etc. In addition, some embodiments may include electronic devices such as computing devices, data server devices, media content storage devices, etc. that comprise the storage media and/or control circuitry as described above.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the embodiments disclosed herein.