Testing circuitry in a stacked semiconductor device using through silicon vias

More than one reissue application has been filed for the reissue of Pat. No. 8,503,261. The reissue applications are application numbers the present application, Ser. No. 13/531,346 (issued as U.S. Pat. No. 8,503,261), Ser. No. 16/780,767 (issued as U.S. Pat. No. RE49390), and Ser. No. 14/820,325 (issued as U.S. Pat. No. RE47840).The present applicationis a reissue continuation of application Ser. No. 16/780,767, which is a reissue divisional of application Ser. No. 14/820,325, which is an application for reissue of U.S. Pat. No. 8,503,261, whichis a Continuation Application of U.S. patent application Ser. No. 12/656,485, filed on Feb. 1, 2010 now U.S. Pat. No. 8,243,486, which is based onJapa-neseJapanesepatent application No. 2009-024486, filed on Feb. 5, 2009, the entire contents of which is incorporated herein by reference.

1. Field of the Invention

This invention relates to a semiconductor device having a DRAM or the like, and particularly to a semiconductor device formed by stacking a plurality of chip dies.

2. Description of the Related Art

An example of this type of semiconductor devices is a semiconductor device in which a memory module is formed by stacking a plurality of DRAM chips on an IO chip mounted on an interposer board and connecting the DRAM chips to the IO chip by means ofthrough electrodesTSVsformed within through silicon vias (Sivia) (see Japanese Laid-Open Patent Publication No. 2004-327474 (Patent Document 1) corresponding to U.S. Pat. No. 7,123,497 (Patent Document 2).

More specifically, according to Patent Document 1, each of the DRAM chips of the memory module has a plurality of vias andthrough electrodesTSVsformed within these vias in order to transfer data signals and data mask signals accompanied by the data signals.

A semiconductor device configured in this manner has advantages that the length of wiring lines connecting a plurality of DRAM chips can be shortened and a DLL, consuming a large amount of current, need be provided only on anIOI/Ochip.

However, Patent Document 1 gives no consideration to the case in which the transfer speed of a data signal output from a semiconductor device having a plurality of DRAM chips stacked is increased. Specifically, Patent Document 1 does not mention problems which may occur when the data transfer speed from the stacked DRAM chips is increased, nor doesit mentionsolutions to such problems. In practice, it has been found that various problems such as increased power consumption anddeteriorateddecreasedyield would occur when the data transfer speed from the DRAM chips is increased.

Considering, for example, a case where a memory module having a total memory capacity of 2 GB (giga bytes) is formed of 16 DRAM chips, the memory module as a whole will have 64 data I/Othrough electrodesTSVsif each DRAM chip has four data I/Othrough electrodesTSVs. If it is assumed here that a data signal is input and output via each of the data I/Othrough electrodesTSVsat a transfer speed of 1600 Mbps, the data signal will be input and output via the data I/Othrough electrodesTSVsat a transfer speed of 102.4 Gbps (i.e., 12.8 GB/s) in the memory module as a whole.

However, if a data signal is input and output to and from the DRAM chips at a data transfer speed of 1600 Mbps, the current consumed by the DRAM chips will be increased significantly, resulting in increased consumption current and noise in the memory module as a whole. Further, in order to realize a data transfer speed as high as 1600 Mbps, the DRAM chips must be operated at a high frequency of 800 MHz even if the DDR (Double Data Rate) technology is employed. Thus, the fabrication of DRAM chips operating at high frequency will impose difficulties in terms of various product specification values (e.g., timing specification), deteriorating the yield of the product. Furthermore, it will make it difficult to ensure stable operation of the memory module during communication with a memory controller. These problems are attributable to the face that as the number of stacked chips is increased, the high frequency operation (at high data transfer rate) is affected more by total parasitic resistance or total parasitic capacitance of the through silicon vias and via-to-via connections proportional to the thickness of the stacked chips.

The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part.

In one embodiment, a method of testing a semiconductor device comprising:

providing a first wafer that comprises a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode;

providing a second wafer that comprises a second electrode penetrating the second wafer;

stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer;

probing a needle to the pad; and

supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

Referring to, a semiconductor device according to a first embodiment of this invention will be described.

The shown semiconductor device has a stacking substrateformed for example of an insulating material, and a plurality of chip dies (first to eighth chip diestoin this example) stacked on one surface of the stacking substrate, whereby a memory module is formed. Although the following description of this exemplary embodiment will be made on the assumption that the chip diestohave a memory function, the chip dies according to this invention are not limited to those having a memory function. There are provided, on the opposite surface of the stacking substrateto the surface where the chip dies are mounted, BGA (Ball Grid Array) terminals for external data signals, address signals, external control signals, and external clock signals, the BGA terminals being arranged corresponding to the mounting pitch on a packaging substrate (not shown) for mounting the semiconductor device The chip dieis generally called as a semiconductor chip by those skilled in the art since it is formed of a semiconductor substrate, particularly of a silicon chip.

AnIOI/Ochip such as a controller for controlling the plurality of chip dies may be provided between the chip dieand the stacking substrate, or, alternatively, the semiconductor device may have only the chip diemounted on the stacking substrate. When anIOI/Ochip is stacked together with the chip diesto, theIOI/Ochip is provided with a memory controller to form a memory system. On the other hand, when a controller is provided in the outside of the stacking substrate (outside the semiconductor device), a memory system is formed by the semiconductor device including the stacked chip dies and the controller provided outside thereof.

Each of the chip diestohas TSVs (Through-Silicon Vias) to be described later, and the chip dies are mutually connected by a technique using bumps or the like related to the TSV technique. The stacking substrateand the chip dies are also mutually connected by means of bumps or the like.

Each of the chip diesto, as shown representatively by the first chip die, has a memory array, a plurality ofIOI/Ocircuits (in this example, 32IOI/Ocircuitsto) connected to the memory array, and a plurality of switches (in this example, eight switchesto,to, . . . ,to) connected to input/output lines extending from theIOI/Ocircuitsto.

In each of the reference numbers indicating these switches, for example in the reference number “”, the most significant digit “1” indicates the number of the corresponding chip die, the first chip die in this case, the least significant digit “0” indicates the number allocated to the switch, and the two digits between the most significant and least significant digits “31” represent the last two digits in the number allocated to the correspondingIOI/Ocircuit, theIOI/Ocircuitin this case.

Eight switches are connected to each input/output line, and the switchesto, for example, are connected tothrough electrodesTSVsprovided within the eight vias Vto V, respectively. Likewise, eight vias Vto Vare provided corresponding to the switchesto, respectively. This applies to the other switches as well, and vias Vto Vare provided corresponding to the switchesto, respectively. Accordingly, there are provided 256 vias in total in the first chip diefor the purpose of data transfer. Vias are also provided for a plurality of control signals as described later, in addition to those for the data transfer (IO signals) but also.

In the example shown in, there are provided ROMstoeach of which is set to select one of the eight switches connected to each input/output line. These ROMstomay be EEPROMs or may be configured as anti-fuses. The same applies to other ROMs to be described later. Although, in this embodiment, the ROMstoare provided respectively corresponding to theIOI/Ocircuitstoin a one-to-one relationship, a single ROM may be provided to cover all the switchestoconnected to theIOI/Ocircuitsto.

Second to eighth chip diestohave the same configuration as that of the first chip die, and have switchesto, . . . , andto, respectively. More specifically, like the first chip die, the second chip dieis provided with 256 (32×8) data transfer vias Vto Vand data transferthrough electrodesTSVsin correspondence with the switchesto. The eighth chip dieis also provided with 256 data transfer vias Vto Vin correspondence with the switchesto.

As mentioned above, the first to eighth chip diestohave the same configuration and thus these chip dies can be manufactured using the same design, the same pattern layout, and the same manufacturing process.

Further, in the example shown in, only one of the eight switches connected to each input/output line is rendered electrically conductive by the ROMsto. In the first chip die, one of each set of the switchesto,to, . . . , andtorespectively connected to theIOI/Ocircuitstois selected to be rendered conductive by the ROMsto. Therefore, in this first chip die, 32 switches are rendered electrically conductive at the same time. This means that 32-bit data signals are simultaneously input and output to and from the first chip die.

In the second to eighth chip diestoas well, like the first chip die, 32 switches are simultaneously rendered conductive by the ROMs, whereas the positions of the 32 switches rendered conductive are different among the chip diesto. For example, the switches,, . . . , andare made conductive in the first chip die, and the switches,, . . . , andare made conductive in the second chip die. The same rule is applied to the other chip dies, and the switches,, . . . , andare made conductive in the eighth chip die.

As a result, in the first chip die, data signals of 32-bit width are transmitted and received via the switches,, . . . , andand the data transfer vias V, V, . . . , and Vcorresponding to these switches. Likewise in the second chip die, data signals are transmitted and received via the switches,, . . . , andand the data transfer vias V, V, . . . , and Vcorresponding to these switches. In the eighth chip die, data signals are transmitted and received via the switches,, . . . , andand the data signal transfer vias V, V, . . . , and Vcorresponding thereto.

The data signal transfer vias provided in the first to eighth chip diestoand connected to the non-conductive switches do not assume any role in the chip dies but only allow data signals from other chip dies to pass through.

Consequently, in the memory module as a whole, data signals (×256-bit data signals) are input and output through the data transferthrough electrodesTSVsformed in 256 vias.

The shown memory module is thus characterized by having a number of vias (e.g., 256 vias) corresponding to the number of stacked chip dies and the number of bits of data signals input and output to and from an external circuit (e.g., a memory controller). As mentioned in the above, the data transferthrough electrodesTSVsformed in the vias function as a single data line no matter how many chip dies are stacked. Although eight chip dies are stacked in this example, the number of stacked chip dies is not limited to eight. When 16 chip dies are stacked, for example, 16 switches and 16through electrodesTSVscorresponding thereto are provided and the switches are controlled in the same manner as described above.

It is assumed here that the data transfer speed of the shown memory module is 12.8 Gbytes/sec (102.4 Gbits), and the memory module has a memory capacity of 2 Gbytes (16 Gbits).

In the memory module shown inhaving eight chip dies, as described above, data signals are transmitted and received through the 256 data transferthrough electrodesTSVsformed in the 256 vias. In this case, each data transferthrough electrodeTSVsonly need be capable of transmitting and receiving data signals at a data transfer rate of 400 Mbps (102.4 Gbit/256). Thus, the data transfer rate of data signals transmitted and received through each data transfer through electrode of the chip diestocan be reduced in comparison with the transfer rate according to the conventional technique by increasing the number of vias the chip diestoaccording to the number of stacked chip dies. This enables the memory module to stably communicate with the memory controller at a low power consumption, and provides a memory module having a data transfer speed of 12.8 Gbytes/sec.

On the other hand, the memory controller has a parallel-serial conversion circuit (not shown). For example, during read data communication from the memory chip dies, the parallel-serial conversion circuit converts data transmitted by the chip dies at 400 Mbps into 1600-Mbps serial data signals and provides the same to a CPU or the like. Further, the memory controller also has a serial-parallel conversion circuit for converting 1600-Mbps serial data signals from the CPU or the like into 400-Mbps parallel data and transmitting the same to the chip dies.

According to the configuration as described above, the chip diestocan be operated at a lower speed compared to the conventional technique, and thus the consumption current can be reduced compared to the conventional chip dies operating at a higher speed. The configuration thus realizes stable communication and improves the manufacturing yield.

When the chip diestoare stacked on an IO chip having a controller (in other words, when at least a plurality of memory chips and a memory controller chip controlling the same are packaged together as a semiconductor device molded using a resin material), the IO chip is provided with the same number of vias as the vias provided in the chip diesto, and the data transferthrough electrodesTSVsformed in these vias on the IO chip are connected to the data transferthrough electrodesTSVsof the chip dies to transmit and receive data signals to and from the controller. The controller has a parallel-serial conversion circuit for parallel-serial converting data signals received from the chip diestothrough the 256 data transferthrough electrodesTSVs, and a serial-parallel conversion circuit for serial-parallel converting data signals from the outside.

In contrast, when noIOI/Ochip is provided (in other words, when a plurality of memory chips are packaged as a semiconductor device molded with a resin material while a memory controller controlling the same is provided as a separate semiconductor device by being packaged separately), the data transfer speed of data signals given through the BGA terminals of the stacking substrateis converted by the controller arranged outside thereof.

Referring to, an electrical circuit configuration of the chip dies (herein, description will be made taking the chip dieas an example). The chip dieshown inhas a memory cell array, and an interface circuitin which the switchesto, IO circuitsto, input/output lines, andthrough electrodesTSVsformed in the vias Vto Vas shown inare integrated. Although the interface circuitactually includes the IO circuitsto, the switchesto, the ROMsto, and thethrough electrodesTSVs(Vto V(DQ)), only the IO circuit, the switch, the ROM, and thethrough electrodeTSVs(DQ)formed in the via Vare shown in the illustrated example for the sake of simplification.

The shown memory cell arrayhas banksto, and sense amplifiers, column decoders, and row decoders connected to the respective banksto. The memory cell arrayis further provided with a row address buffer and refresh counter and a column address buffer and burst counter for receiving address signals Ato Aand bank addresses BAto BAsupplied from the outside, and with a mode register.

Further, a command decoder and a control logic circuit are provided for receiving command signals /CS, /RAS, /CAS, and /WE supplied from the outside. The command decoder and the control logic circuit are supplied with clock signals from a clock generator.

The shown chip diehas the interface circuit, as described above, arranged between the memory cell arrayand the data transferthrough electrodesTSVs(DQ). This interface circuitis connected to the column decoders via a latch circuit and a data control circuit. The latch circuit and the data control circuit are controlled by the control logic circuit. The clock signals from the clock generator are also supplied to the column decoder and the latch circuit.

The shown interface circuithas all of the IO circuits, ROMs, switches, and data transferthrough electrodesTSVsshown in. The interface circuitis further provided with terminals for on-die termination signals (ODT) and data mask signals (DM), a terminal for data strobe signals (DQS,/DQS), and a terminal for RDQS,/RDQS.

The components of the memory cell array, such as the banksto, the column decoders, and the row decoders may be those used in conventional DRAMs. Accordingly, description thereof will be omitted here.

Although only the chip dieis illustrated in, the other chip diestoalso have the same configuration as the chip die.

Referring to, a semiconductor device according to a second embodiment of this invention will be described. The semiconductor device shown inis a memory module including first to sixteenth chip dies Dto D. Each of the chip dies Dto Dhas 256 data transferthrough electrodesTSVs(i.e., DQ pins), in the same manner as the semiconductor device according to the first embodiment shown inin this respect. Accordingly, like the one in the first embodiment, this memory device is also capable of transferring data at a low speed from the chip dies Dto Dthrough the 256 data transferthrough electrodesTSVs, and the power consumption of the memory module can be reduced.

However, the memory module according to the second embodiment shown inis different from the memory module of the first embodiment in the fact that the number of chip dies is doubled compared to the first embodiment and sixteen chip dies Dto Dare provided.

Describing more specifically, in the memory module shown in, the first to sixteenth chip dies Dto Dare divided into first and second groups, so that the first and second groups are switched over by using system control signals Cand C. Specifically, the first group is composed of the first to seventh chip dies Dto D, and the second group is composed of the eighth to sixteenth chip dies Dto D.